Ramesh Harjani

176 papers A* 5A 18B 2C 11Misc 11Journal 52Unranked 76

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A DTC-Based Snapshot ADPLL With Feedforward Fractional Spur Cancellation and Asynchronous Duty-Modulation Dithering DCO Achieving-71.6 dBc Fractional Spur in 65-nm CMOS Process. IEEE Access Kihoon Kwon, Sangwon Kim, Minseo Park, Jinhyuk Ahn, Gahyeon Lee, Joonho Gil, Chulhyun Park, Yunseong Eo, Hyungkyu Choi, Chulho Kang, Eun Seong Kim, Nam-Young Kim, Ramesh Harjani, Taehyoun Oh
2026	J	`jnl`	COmPOSER: Circuit Optimization of mm-wave/RF circuits with Performance-Oriented Synthesis for Efficient Realizations. CoRR Subhadip Ghosh, Surya Srikar Peri, S. Ramprasath, Sosina A. Berhan, Endalk Y. Gebru, Ramesh Harjani, Sachin S. Sapatnekar
2025	J	`jnl`	A 8.9 to 10-GHz -97.86-dBc Reference Spur Pulser-Free Continuous Charge Pump Sub-Sampling PLL With Fine-Tunable Dead-Zone Generator in 65-nm CMOS Process. IEEE Access Sangwon Kim, Kihoon Kwon, Minseo Park, Jinhyuk Ahn, Junseo Kim, Joonho Gil, Chulhyun Park, Yunseong Eo, Ramesh Harjani, Taehyoun Oh
2025	A	`conf`	Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables. DATE Subhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap, Ramesh Harjani, Sachin S. Sapatnekar
2025	J	`jnl`	Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables. CoRR Subhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap, Ramesh Harjani, Sachin S. Sapatnekar
2025	A*	`conf`	Invited: EDA for Heterogeneous Integration. DAC Emad Haque, Pragnya Sudershan Nalla, Chetal Choppali Sudarshan, Divya Yogi, Hangyu Zhang, Chaitali Chakrabarti, Vidya A. Chhabria, Ramesh Harjani, Jeff Zhang, Sachin S. Sapatnekar
2025	J	`jnl`	Minimum Unit Capacitance Calculation for Capacitor Arrays in Binary-Weighted and Split DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar
2025	A	`conf`	Optimal Selection and Placement of Voltage Regulators in 2.5D Heterogeneously Integrated Systems. ICCAD Hangyu Zhang, Divya Yogi, Ramesh Harjani, Sachin S. Sapatnekar
2024	J	`jnl`	A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process. IEEE Access Kyoung-Ub Cho, Joonho Gil, Chulhyun Park, Kyu-Jin Cho, Jae-Woo Shin, Eun Seong Kim, Yun Seong Eo, Ramesh Harjani, Nam-Young Kim, Taehyoun Oh
2024	—	`conf`	An Efficient Real-Valued Cross-Correlator via Fast Fourier Transform. SiPS Sin-Wei Chiu, Ramesh Harjani, Keshab K. Parhi
2024	A	`conf`	Analyzing the Impact of FinFET Self-Heating on the Performance of RF Power Amplifiers. ICCAD Nibedita Karmokar, Sai-Wang Tam, Thanh Viet Dinh, Vidya A. Chhabria, Ramesh Harjani, Sachin S. Sapatnekar
2024	B	`conf`	Automated synthesis of mixed-signal ML inference hardware under accuracy constraints. ASPDAC Kishor Kunal, Jitesh Poojary, S. Ramprasath, Ramesh Harjani, Sachin S. Sapatnekar
2024	J	`jnl`	Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar
2024	J	`jnl`	MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2024	J	`jnl`	Monitoring Water Level Fluctuations of Reservoirs in the Krishna River Basin Using Sentinel-3 and ICESat-2 Altimetry Data. IEEE Access Ahalya Nalluri, Ramesh Harjani, Pankaj Ramji Dhote
2024	B	`conf`	Reinforcing the Connection between Analog Design and EDA (Invited Paper). ASPDAC Kishor Kunal, Meghna Madhusudan, Jitesh Poojary, S. Ramprasath, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar
2023	J	`jnl`	A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. ACM Trans. Design Autom. Electr. Syst. Ramprasath Srinivasa Gopalakrishnan, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
2023	A	`conf`	AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit Cells. DATE Sumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun
2023	J	`jnl`	Constructive Placement and Routing for Common-Centroid Capacitor Arrays in Binary-Weighted and Split DACs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2023	J	`jnl`	GNN-Based Hierarchical Annotation for Analog Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2023	—	`conf`	MMM: Machine Learning-Based Macro-Modeling for Linear Analog ICs and ADC/DACs. MLCAD Yishuang Lin, Yaguang Li, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2023	A	`conf`	Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor Arrays. DATE Nibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar
2023	J	`jnl`	Performance-driven Wire Sizing for Analog Integrated Circuits. ACM Trans. Design Autom. Electr. Syst. Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2023	—	`conf`	Understanding Distance-Dependent Variations for Analog Circuits in a FinFET Technology. ESSDERC Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Ramprasath S, Kishor Kunal, Sachin S. Sapatnekar, Ramesh Harjani
2022	A	`conf`	A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. DATE Tonmoy Dhar, Ramprasath S, Jitesh Poojary, Soner Yaldiz, Steven M. Burns, Ramesh Harjani, Sachin S. Sapatnekar
2022	—	`conf`	Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. ISPD Ramprasath S, Meghna Madhusudan, Arvind K. Sharma, Jitesh Poojary, Soner Yaldiz, Ramesh Harjani, Steven M. Burns, Sachin S. Sapatnekar
2022	A	`conf`	Are Analytical Techniques Worthwhile for Analog IC Placement? DATE Yishuang Lin, Yaguang Li, Donghao Fang, Meghna Madhusudan, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2022	—	`conf`	Common-Centroid Layout for Active and Passive Devices: A Review and the Road Ahead. ASP-DAC Nibedita Karmokar, Meghna Madhusudan, Arvind K. Sharma, Ramesh Harjani, Mark Po-Hung Lin, Sachin S. Sapatnekar
2022	A	`conf`	Constructive Common-Centroid Placement and Routing for Binary-Weighted Capacitor Arrays. DATE Nibedita Karmokar, Arvind K. Sharma, Jitesh Poojary, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2022	J	`jnl`	Linear Characteristic Analysis of High-Resolution Counter-Based Frequency Detector in Type-I Digital PLL. IEEE Trans. Circuits Syst. II Express Briefs Taehyoun Oh, Joonho Gil, Ramesh Harjani
2022	J	`jnl`	Pseudo-Reference Counter-Based FLL for 6 Gb/s Reference-Less CDR in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Sanggeun Lee, Ramesh Harjani, Taehyoun Oh
2021	—	`conf`	6.4 A 1-to-3GHz Co-Channel Blocker Resistant, Spatially and Spectrally Passive MIMO Receiver in 65nm CMOS with +6dBm In-Band/In-Notch B1dB. ISSCC Jitesh Poojary, Ramesh Harjani
2021	—	`conf`	A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. MLCAD Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2021	J	`jnl`	ALIGN: A System for Automating Analog Layout. IEEE Des. Test Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2021	—	`conf`	Aging of Current DACs and its Impact in Equalizer Circuits. IRPS Tonmoy Dhar, Jitesh Poojary, Ramesh Harjani, Sachin S. Sapatnekar
2021	A	`conf`	Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. DATE Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Parijat Mukherjee, Soner Yaldiz, Ramesh Harjani, Sachin S. Sapatnekar
2021	—	`conf`	Fast and Efficient Constraint Evaluation of Analog Layout Using Machine Learning Models. ASP-DAC Tonmoy Dhar, Jitesh Poojary, Yaguang Li, Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Susmita Dey Manasi, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2021	A	`conf`	From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen
2021	—	`conf`	Machine Learning Techniques in Analog Layout Automation. ISPD Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2021	A	`conf`	Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. ICCAD Arvind K. Sharma, Meghna Madhusudan, Steven M. Burns, Soner Yaldiz, Parijat Mukherjee, Ramesh Harjani, Sachin S. Sapatnekar
2021	—	`conf`	SE3: Favorite Circuit Design and Testing Mistakes of Starting Engineers. ISSCC Ramesh Harjani, Mike Chen, Marco Berkhout, Johan H. C. van den Heuvel, Thomas H. Lee, Robert Bogdan Staszewski, Kathleen Philips, Howard C. Luong, Vadim Ivanov
2020	A	`conf`	A Customized Graph Neural Network Model for Guiding Analog IC Placement. ICCAD Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2020	A	`conf`	A general approach for identifying hierarchical symmetry constraints for analog circuit layout. ICCAD Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2020	J	`jnl`	A general approach for identifying hierarchical symmetry constraints for analog circuit layout. CoRR Kishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar
2020	J	`jnl`	ALIGN: A System for Automating Analog Layout. CoRR Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Sachin S. Sapatnekar, Soner Yaldiz
2020	—	`book`	Design of Low Power Integrated Radios for Emerging Standards Mustafijur Rahman, Ramesh Harjani
2020	—	`conf`	Exploring a Machine Learning Approach to Performance Driven Analog IC Placement. ISVLSI Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Sachin S. Sapatnekar, Ramesh Harjani, Jiang Hu
2020	A	`conf`	GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. DATE Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar
2020	J	`jnl`	Jitter Suppression Techniques for High-Speed Sample-and-Hold Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. Shiva Jamali-Zavareh, Ramesh Harjani
2020	—	`conf`	Learning from Experience: Applying ML to Analog Circuit Design. ISPD Kishor Kunal, Tonmoy Dhar, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Sachin S. Sapatnekar
2020	A	`conf`	The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). ICCAD Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar
2019	J	`jnl`	A 0.4-1.0 GHz, 47 MHop/s Frequency-Hopped TXR Front End With 20 dB In-Band Blocker Rejection. IEEE J. Solid State Circuits Naser Mousavi, Zhiheng Wang, Danijela Cabric, Ramesh Harjani
2019	—	`conf`	A Multi-Mode DC-DC Converter for Direct Battery-to-Silicon High Tension Power Delivery in 65nm CMOS. CICC Saurabh Chaubey, Ramesh Harjani
2019	A*	`conf`	ALIGN: Open-Source Analog Layout Automation from the Ground Up. DAC Kishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar
2019	—	`conf`	Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators. MWSCAS Saurabh Chaubey, Meghna Madhusudan, Ramesh Harjani
2018	—	`conf`	A 0.4-1.0GHz, 47MHop/S Frequency Hopped TXR Front-End with 20dB in-Band Blocker Rejection. ESSCIRC Naser Mousavi, Zhiheng Wang, Ramesh Harjani
2018	—	`conf`	A 100MS/s 9-bit Companding SAR ADC with On-Chip Input Driver in 65nm CMOS for Multi-Carrier Communications. MWSCAS Anindya Saha, Saurabh Chaubey, Ramesh Harjani
2018	J	`jnl`	A 2.4-GHz, Sub-1-V, 2.8-dB NF, 475-µW Dual-Path Noise and Nonlinearity Cancelling LNA for Ultra-Low-Power Radios. IEEE J. Solid State Circuits Mustafijur Rahman, Ramesh Harjani
2018	—	`conf`	A 2.4GHz IEEE 802.15.6 Compliant 1.52nJ/bit TX & 1.32nJ/bit RX Multiband Transceiver for Low Power Standards. ICECS Mustafijur Rahman, Ramesh Harjani
2018	—	`conf`	A 4GHz Instantaneous Bandwidth Low Squint Phased Array Using Sub-Harmonic ILO Based Channelization. ESSCIRC Qingrui Meng, Ramesh Harjani
2018	—	`conf`	A 5μW-5mW input power range, 0-3.5V output voltage range RF energy harvester with power-estimator-enhanced MPPT controller. CICC Xingyi Hua, Ramesh Harjani
2017	—	`conf`	A smart-offset analog LDO with 0.3V minimum input voltage and 99.1% current efficiency. A-SSCC Saurabh Chaubey, Ramesh Harjani
2017	J	`jnl`	An Overview of Time-Based Computing with Stochastic Constructs. IEEE Micro M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani
2017	—	`conf`	Fully tunable software defined DC-DC converter with 3000X output current & 4X output voltage ranges. CICC Saurabh Chaubey, Ramesh Harjani
2017	—	`conf`	Integrated DC-DC converter design. CICC Ramesh Harjani
2017	J	`jnl`	Low-Power Wideband Analog Channelization Filter Bank Using Passive Polyphase-FFT Techniques. IEEE J. Solid State Circuits Hundo Shin, Ramesh Harjani
2017	J	`jnl`	Time-Encoded Values for Highly Efficient Stochastic Circuits. IEEE Trans. Very Large Scale Integr. Syst. M. Hassan Najafi, Shiva Jamali-Zavareh, David J. Lilja, Marc D. Riedel, Kia Bazargan, Ramesh Harjani
2016	—	`conf`	A 1GHz signal bandwidth 4-channel-I/Q polyphase-FFT filter bank. ESSCIRC Hundo Shin, Ramesh Harjani
2016	—	`conf`	A jitter-resilient sampling technique for high-resolution ADCs in wideband RF receivers. ICECS Shiva Jamali-Zavareh, Ramesh Harjani
2016	—	`conf`	An easily extendable FFT based four-channel, four-beam receiver with progressive partial spatial filtering in 65nm. ESSCIRC Qingrui Meng, Ramesh Harjani
2016	—	`conf`	CMOS energy efficient integrated radios for emerging low power standards. ISOCC Mustafijur Rahman, Ramesh Harjani
2015	—	`conf`	3.5-0.5V input, 1.0V output multi-mode power transformer for a supercapacitor power source with a peak efficiency of 70.4%. CICC Xingyi Hua, Ramesh Harjani
2015	J	`jnl`	A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Rakesh Kumar Palani, Ramesh Harjani
2015	—	`conf`	A 4.6mW, 22dBm IIP3 all MOSCAP based 34-314MHz tunable continuous time filter in 65nm. CICC Rakesh Kumar Palani, Ramesh Harjani
2015	—	`conf`	A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS. VLSIC Fang-Li Yuan, Rakesh Kumar Palani, Sina Basir-Kazeruni, Hundo Shin, Anindya Saha, Ramesh Harjani, Dejan Markovic
2015	J	`jnl`	An IEEE 802.15.6 Standard Compliant 2.5 nJ/Bit Multiband WBAN Transmitter Using Phase Multiplexing and Injection Locking. IEEE J. Solid State Circuits Mustafijur Rahman, Mohammad Elbadry, Ramesh Harjani
2015	—	`conf`	An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS. CICC Hundo Shin, Rakesh Kumar Palani, Anindya Saha, Fang-Li Yuan, Dejan Markovic, Ramesh Harjani
2015	—	`conf`	Chopper stabilized sub 1V reference voltage in 65nm CMOS. MWSCAS Rakesh Kumar Palani, Aravindhan Rangarajan, Ramesh Harjani
2015	—	`conf`	Design of PVT tolerant inverter based circuits for low supply voltages. CICC Ramesh Harjani, Rakesh Kumar Palani
2015	J	`jnl`	Wideband blind signal classification on a battery budget. IEEE Commun. Mag. Ramesh Harjani, Danijela Cabric, Dejan Markovic, Brian M. Sadler, Rakesh Kumar Palani, Anindya Saha, Hundo Shin, Eric Rebeiz, Sina Basir-Kazeruni, Fang-Li Yuan
2014	—	`conf`	A 52% tuning range QVCO with a reduced noise coupling scheme and a minimum FOMT of 196dBc/Hz. CICC Mohammad Elbadry, Sachin Kalia, Ramesh Harjani
2014	—	`conf`	A unified framework for capacitive series-parallel DC-DC converter design. CICC Ramesh Harjani, Saurabh Chaubey
2014	J	`jnl`	Building an on-chip spectrum sensor for cognitive radios. IEEE Commun. Mag. Bodhisatwa Sadhu, Martin Sturm, Brian M. Sadler, Ramesh Harjani
2014	—	`conf`	High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS. CICC Rakesh Kumar Palani, Ramesh Harjani
2014	—	`conf`	High power-density, hybrid inductive/capacitive converter with area reuse for multi-domain DVS. CICC Sudhir S. Kudva, Saurabh Chaubey, Ramesh Harjani
2013	J	`jnl`	A 12-Gb/s Multichannel I/O Using MIMO Crosstalk Cancellation and Signal Reutilization in 65-nm CMOS. IEEE J. Solid State Circuits Taehyoun Oh, Ramesh Harjani
2013	J	`jnl`	A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
2013	J	`jnl`	A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J. Solid State Circuits Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
2013	J	`jnl`	Analysis and Design of a 5 GS/s Analog Charge-Domain FFT for an SDR Front-End in 65 nm CMOS. IEEE J. Solid State Circuits Bodhisatwa Sadhu, Martin Sturm, Brian M. Sadler, Ramesh Harjani
2013	J	`jnl`	Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". IEEE J. Solid State Circuits Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
2013	J	`jnl`	Fully Integrated Capacitive DC-DC Converter With All-Digital Ripple Mitigation Technique. IEEE J. Solid State Circuits Sudhir S. Kudva, Ramesh Harjani
2013	J	`jnl`	Multi-Beam Spatio-Spectral Beamforming Receiver for Wideband Phased Arrays. IEEE Trans. Circuits Syst. I Regul. Pap. Sachin Kalia, Satwik A. Patnaik, Bodhisatwa Sadhu, Martin Sturm, Mohammad Elbadry, Ramesh Harjani
2012	—	`conf`	4×12 Gb/s 0.96 pJ/b/lane analog-IIR crosstalk cancellation and signal reutilization receiver for single-ended I/Os in 65 nm CMOS. VLSIC Taehyoun Oh, Ramesh Harjani
2012	—	`conf`	A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. CICC Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
2012	—	`conf`	A 5-300MHz CMOS transceiver for multi-nuclear NMR spectroscopy. CICC Jaehyup Kim, Bruce Hammer, Ramesh Harjani
2012	—	`conf`	An 8GHz multi-beam spatio-spectral beamforming receiver using an all-passive discrete time analog baseband in 65nm CMOS. CICC Satwik A. Patnaik, Sachin Kalia, Bodhisatwa Sadhu, Martin Sturm, Mohammad Elbadry, Ramesh Harjani
2012	—	`conf`	Fully integrated capacitive converter with all digital ripple mitigation. CICC Sudhir S. Kudva, Ramesh Harjani
2012	—	`conf`	Radio receiver techniques. CICC Alberto Valdes-Garcia, Ramesh Harjani
2011	J	`jnl`	A 6-Gb/s MIMO Crosstalk Cancellation Scheme for High-Speed I/Os. IEEE J. Solid State Circuits Taehyoun Oh, Ramesh Harjani
2011	J	`jnl`	Frequency-Hopped Quadrature Frequency Synthesizer in 0.13-mum Technology. IEEE J. Solid State Circuits Narasimha Lanka, Satwik A. Patnaik, Ramesh Harjani
2011	J	`jnl`	Fully-Integrated On-Chip DC-DC Converter With a 450X Output Range. IEEE J. Solid State Circuits Sudhir S. Kudva, Ramesh Harjani
2010	J	`jnl`	A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links. IEEE J. Solid State Circuits Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani
2010	—	`conf`	A 5Gb/s 2×2 MIMO crosstalk cancellation scheme for high-speed I/Os. CICC Taehyoun Oh, Ramesh Harjani
2010	C	`conf`	Capacitor bank design for wide tuning range LC VCOs: 850MHz-7.1GHz (157%). ISCAS Bodhisatwa Sadhu, Ramesh Harjani
2010	—	`conf`	Fully integrated on-chip DC-DC converter with a 450x output range. CICC Sudhir S. Kudva, Ramesh Harjani
2009	—	`conf`	A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links. CICC Mahmoud Reza Ahmadi, Amir Amirkhany, Ramesh Harjani
2009	—	`conf`	A CMOS 3.3-8.4 GHz wide tuning range, low phase noise LC VCO. CICC Bodhisatwa Sadhu, Jaehyup Kim, Ramesh Harjani
2009	—	`conf`	A dual-mode architecture for a phased-array receiver based on injection locking in 0.13µm CMOS. ISSCC Satwik A. Patnaik, Narasimha Lanka, Ramesh Harjani
2009	—	`conf`	A sub-2.5ns frequency-hopped quadrature frequency synthesizer in 0.13-μm technology. CICC Narasimha Lanka, Satwik A. Patnaik, Ramesh Harjani
2009	J	`jnl`	Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs. IEEE Trans. Very Large Scale Integr. Syst. Jie Gu, Ramesh Harjani, Chris H. Kim
2009	—	`conf`	Millimeter-wave ICs. CICC Ramesh Harjani, Alireza Shirvani Marvell
2008	J	`jnl`	A 3, times, 5-Gb/s Multilane Low-Power 0.18-muhbox m CMOS Pseudorandom Bit Sequence Generator. IEEE Trans. Circuits Syst. II Express Briefs Kin-Joe Sham, Shubha Bommalingaiahnapallya, Mahmoud Reza Ahmadi, Ramesh Harjani
2008	J	`jnl`	A High-Efficiency DC-DC Converter Using 2 nH Integrated Inductors. IEEE J. Solid State Circuits Josh Wibben, Ramesh Harjani
2008	J	`jnl`	Constrained Partial Response Receivers for High-Speed Links. IEEE Trans. Circuits Syst. II Express Briefs Mahmoud Reza Ahmadi, Jaekyun Moon, Ramesh Harjani
2008	—	`conf`	Modeling and synthesis of wide-band switched-resonators for VCOs. CICC Bodhisatwa Sadhu, Umaikhe E. Omole, Ramesh Harjani
2008	—	`conf`	Modeling, measurement and mitigation of crosstalk noise coupling in 3D-ICs. CICC Liuchun Cai, Ramesh Harjani
2008	—	`conf`	Session 19 - Low power and non-traditional RF tranceivers. CICC Ramesh Harjani, Andrea Mazzanti
2007	C	`conf`	High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator. ISCAS Shubha Bommalingaiahnapallya, Kin-Joe Sham, Mahmoud Reza Ahmadi, Ramesh Harjani
2007	—	`conf`	Understanding the Transient Behavior of Injection Locked LC Oscillators. CICC Narasimha Lanka, Satwik A. Patnaik, Ramesh Harjani
2006	—	`conf`	FEXT Crosstalk Cancellation for High-Speed Serial Link Design. CICC Kin-Joe Sham, Mahmoud Reza Ahmadi, S. B. Gerry Talbot, Ramesh Harjani
2006	J	`jnl`	Gain Calibration Technique for Increased Resolution in FRC Data Converters. IEEE Trans. Circuits Syst. II Express Briefs Frank R. Dropps, Ramesh Harjani
2005	J	`jnl`	A high-efficiency CMOS +22-dBm linear power amplifier. IEEE J. Solid State Circuits Yongwang Ding, Ramesh Harjani
2005	J	`jnl`	A new noncoherent UWB impulse radio receiver. IEEE Commun. Lett. Mi-Kyung Oh, Byunghoo Jung, Ramesh Harjani, Dong-Jo Park
2005	—	`conf`	Clocking circuits for wireline communications. CICC Jafar Savoj, Ramesh Harjani
2005	Misc	`conf`	High-Speed Interconnect Technology: On-Chip and Off-Chip. VLSI Design Sachin S. Sapatnekar, Jaijeet S. Roychowdhury, Ramesh Harjani
2005	—	`conf`	Power optimized LC VCO and mixer co-design. ISCAS (5) Byunghoo Jung, Shubha Bommalingaiahnapallya, Ramesh Harjani
2005	—	`conf`	Process tolerant design of N-tone Sigma-Delta converters. ISCAS (5) Shubha Bommalingaiahnapallya, Ramesh Harjani
2005	—	`conf`	Pulse generator design for UWB IR communication systems. ISCAS (5) Byunghoo Jung, Yi-Hung Tseng, Jackson Harvey, Ramesh Harjani
2004	—	`conf`	A CMOS high efficiency +22 dBm linear power amplifier. CICC Yongwang Ding, Ramesh Harjani
2004	—	`conf`	A digital DFT technique for verifying the static performance of A/D converters. CICC Wooyoung Choi, Bapiraju Vinnakota, Ramesh Harjani
2004	—	`conf`	A wide tuning range VCO using capacitive source degeneration. ISCAS (4) Byunghoo Jung, Ramesh Harjani
2004	Misc	`conf`	Analog/RF Physical Layer Issues For UWB Systems. VLSI Design Ramesh Harjani, Jackson Harvey, Robert Sainati
2004	—	`conf`	Enhanced analytic noise model for RF CMOS design. CICC Jim Koeppe, Ramesh Harjani
2004	—	`conf`	Low power implementation of an n-tone Sigma Delta converter. ISCAS (1) Shubha Bommalingaiahnapallya, Ramesh Harjani
2004	—	`conf`	On the selection of on-chip inductors for the optimal VCO design. CICC Yong Zhan, Ramesh Harjani, Sachin S. Sapatnekar
2004	J	`jnl`	ΣHigh-frequency LC VCO design using capacitive degeneration. IEEE J. Solid State Circuits Byunghoo Jung, Ramesh Harjani
2003	—	`conf`	A novel noise optimization design technique for radio frequency low noise amplifiers. ISCAS (1) Byunghoo Jung, Anand Gopinath, Ramesh Harjani
2003	—	`conf`	Novel integratable notch filter implementation for 100 dB image rejection. ISCAS (1) Deepa S. Parthasarathy, Ramesh Harjani
2001	J	`jnl`	A 455-Mb/s MR preamplifier design in a 0.8-μm CMOS process. IEEE J. Solid State Circuits Ramesh Harjani
2001	—	`conf`	An ISM band CMOS integrated transceiver design for wireless telemetry system. ISCAS (4) Jonghae Kim, Ramesh Harjani
2001	Misc	`conf`	An Integrated Quadrature Mixer with Improved Image Rejection at Low Voltage. VLSI Design Jackson Harvey, Ramesh Harjani
2001	—	`conf`	Analysis and gain design of an integrated quadrature mixer with improved noise and image rejection. ISCAS (4) Jackson Harvey, Ramesh Harjani
2001	—	`conf`	Capacitive voltage multipliers: a high efficiency method to generate multiple on-chip supply voltages. ISCAS (1) Ron Balczewski, Ramesh Harjani
2001	—	`conf`	Non-ideal amplifier effects on the accuracy of analog-to-digital capacitor ratio converter. ISCAS (1) Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota
2001	—	`conf`	Power optimization of CMOS LC VCOs. ISCAS (4) Ming-Ta Hsieh, Jackson Harvey, Ramesh Harjani
2001	Misc	`conf`	Tutorial: CMOS Analog Circuits for Wireless Communications. VLSI Design Ramesh Harjani, Jackson Harvey
2000	C	`conf`	A high speed differential to single-ended amplifier for instrumentation applications. ISCAS Doug Dean, Ramesh Harjani
2000	C	`conf`	A universal analytic charge injection model. ISCAS Yongwang Ding, Ramesh Harjani
2000	C	`conf`	An IF stage design for an ASK-based wireless telemetry system. ISCAS Ramesh Harjani, Oyvind Birkenes, Jonghae Kim
2000	Misc	`conf`	Analog Circuits for Wireless Communications. VLSI Design Ramesh Harjani
2000	A	`conf`	Analysis and design of low-phase-noise ring oscillators. ISLPED Liang Dai, Ramesh Harjani
2000	J	`jnl`	CMOS switched-op-amp-based sample-and-hold circuit. IEEE J. Solid State Circuits Liang Dai, Ramesh Harjani
2000	C	`conf`	Comparison and analysis of phase noise in ring oscillators. ISCAS Liang Dai, Ramesh Harjani
2000	J	`jnl`	DFT for digital detection of analog parametric faults in SC filters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Bapiraju Vinnakota, Ramesh Harjani
2000	—	`conf`	Optimal test-set generation for parametric fault detection in switched capacitor filters. Asian Test Symposium Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota
1999	—	`conf`	A telemetry and interface circuit for piezoelectric sensors. ISCAS (5) Kavita Nair, Ramesh Harjani
1999	Misc	`conf`	Compact, Ultra Low Power, Programmable Continuous-Time Filter Banks for Feedback Cancellation in Hearing Aid. VLSI Design Kavita Nair, Ramesh Harjani
1999	A*	`conf`	Digital Aetection of Analog Parametric Faults in SC Filters. DAC Ramesh Harjani, Bapiraju Vinnakota
1999	—	`conf`	Digital detection of parametric faults in data converters. CICC Bapiraju Vinnakota, Ramesh Harjani
1997	Misc	`conf`	Pseudoduplication - An ACOB Technique for Single-Ended Circuits. VLSI Design Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi
1997	Misc	`conf`	T5: Low-Power Design. VLSI Design Kaushik Roy, Rabindra K. Roy, Ramesh Harjani, K. S. Murthy
1996	Misc	`conf`	Mixed-Signal Design for Test. VLSI Design Bapiraju Vinnakota, Ramesh Harjani
1996	J	`jnl`	System-level design for test of fully differential analog circuits. IEEE J. Solid State Circuits Nicholas J. Stessman, Bapiraju Vinnakota, Ramesh Harjani
1995	C	`conf`	Dynamic Amplifiers: Settling, Slewing and Power Issues. ISCAS Feng Wang, Ramesh Harjani
1995	A*	`conf`	System-Level Design for Test of Fully Differential Analog Circuits. DAC Bapiraju Vinnakota, Ramesh Harjani, Nicholas J. Stessman
1994	C	`conf`	A 6-Bit 50MHz Current-Subtracting Two Step Flash Converter. ISCAS Andrew Cable, Ramesh Harjani
1994	Misc	`conf`	Analog circuit observer blocks. VTS Ramesh Harjani, Bapiraju Vinnakota
1994	A	`conf`	Macromodeling of analog circuits for hierarchical circuit design. ICCAD Jianfeng Shao, Ramesh Harjani
1994	Misc	`conf`	The Design of Analog Self-Checking Circuits. VLSI Design Bapiraju Vinnakota, Ramesh Harjani
1993	C	`conf`	A Dual Frequency Range Integrated Circuit Accelerometer Using Capacitive and Piezoelectric Sensing Techniques. ISCAS Brian A. Blow, Ramesh Harjani, Dennis L. Polla, Takashi Tamagawa
1993	—	`conf`	Acoustic feedback cancellation in hearing aids. ICASSP (1) Rongtai Wang, Ramesh Harjani
1993	C	`conf`	Suppression of acoustic oscillations in hearing aids using minimum phase techniques. ISCAS Rongtai Wang, Ramesh Harjani
1989	J	`jnl`	OASYS: a framework for analog circuit synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
1988	C	`conf`	Analog circuit synthesis and exploration in OASYS. ICCD Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
1988	A	`conf`	Analog circuit synthesis for performance in OASYS. ICCAD Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley
1987	A*	`conf`	A Prototype Framework for Knowledge-Based Analog Circuit Synthesis. DAC Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley