Ramesh C. Tekumalla

22 papers A 6C 1Misc 7Journal 2Unranked 6
YearRankTypeTitle / Venue / Authors
2018 Misc conf
Innovative practices on memory test practice.
VTS
M. Casarsa, Gurgen Harutyunyan, Kaitlyn Chen, Ramesh Sharma, Giri Podichetty, Martin Keim, Sreejit Chakravarty, Ramesh C. Tekumalla
2015 — conf
Clock Domain Imbalances and Their Impact on Test Architecture.
NATW
Ramesh C. Tekumalla
2014 Misc conf
Innovative practices session 1C: Existing/emerging low power techniques.
VTS
Charutosh Dixit, Ramesh C. Tekumalla, Wei Zhao, Nilanjan Mukherjee, Vivek Chickermane
2014 — conf
Local Repair Signature Handling for Repairable Memories.
NATW
Ramesh C. Tekumalla, Prakash Krishnamoorthy
2014 — conf
On Handling Memory Scan Chains.
NATW
Surbhi Bansal, Aviansh Mendhalkar, Ramesh C. Tekumalla
2014 — conf
On-chip Clock Testing and Frequency Measurement.
NATW
Ramesh C. Tekumalla, Prakash Krishnamoorthy
2013 Misc conf
Innovative practices session 2C: Memory test.
VTS
Charutosh Dixit, Ramesh C. Tekumalla, Sreejit Chakravarty, Manuel d'Abreu, Zhuoyu Bao, Concetta Riccobene
2013 — conf
Power aware transformation of bandlimited signals.
SoCC
Prakash Krishnamoorthy, Ramesh C. Tekumalla
2013 — conf
Quotient prediction for low power division.
SoCC
Prakash Krishnamoorthy, Ramesh C. Tekumalla
2006 Misc conf
An On-Chip Diagnosis Methodology for Embedded Cores with Replaceable Modules.
VLSI Design
Ramesh C. Tekumalla
2003 A conf
On Reducing Aliasing Effects and Improving Diagnosis of Logic BIST Failures.
ITC
Ramesh C. Tekumalla
2002 A conf
On Identifying Indistinguishable Path Delay Faults and Improving Diagnosis.
ITC
Ramesh C. Tekumalla, Scott Davidson
2001 J jnl
Identification of primitive faults in combinational and sequentialcircuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ramesh C. Tekumalla, Premachandran R. Menon
2001 Misc conf
On Diagnosing Path Delay Faults in an At-Speed Environment.
VTS
Ramesh C. Tekumalla, Srikanth Venkataraman, Jayabrata Ghosh-Dastidar
2000 J jnl
On Redundant Path Delay Faults in Synchronous Sequential Circuits.
IEEE Trans. Computers
Ramesh C. Tekumalla, Premachandran R. Menon
2000 Misc conf
On Test Set Generation for Efficient Path Delay Fault Diagnosis.
VTS
Ramesh C. Tekumalla
1999 A conf
Robust testability of primitive faults using test points.
ITC
Ramesh C. Tekumalla, Premachandran R. Menon
1998 A conf
On primitive fault test generation in non-scan sequential circuits.
ICCAD
Ramesh C. Tekumalla, Premachandran R. Menon
1997 A conf
Delay Testing with Clock Control: An Alternative to Enhanced Scan.
ITC
Ramesh C. Tekumalla, Premachandran R. Menon
1997 C conf
Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan.
ICCD
Ramesh C. Tekumalla, Premachandran R. Menon
1997 A conf
Test generation for primitive path delay faults in combinational circuits.
ICCAD
Ramesh C. Tekumalla, Premachandran R. Menon
1996 Misc conf
Identifying Redundant Path Delay Faults in Sequential Circuits.
VLSI Design
Ramesh C. Tekumalla, Premachandran R. Menon