Ramchan Woo - RankMe

16 papers C 1Journal 7Unranked 8

Year	Rank	Type	Title / Venue / Authors
2010	—	`conf`	High-speed image sensor technologies. ISSCC Johannes Solhusvik, Jung-Chak Ahn, Jan T. Bosiers, Boyd Fowler, Makoto Ikeda, Shoji Kawahito, Jerry Lin, Dan McGrath, Katsu Nakamura, Jun Ohta, Ramchan Woo
2006	J	`jnl`	A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications. IEEE J. Solid State Circuits Ju-Ho Sohn, Jeong-Ho Woo, Min-wuk Lee, Hyejung Kim, Ramchan Woo, Hoi-Jun Yoo
2005	—	`conf`	A fixed-point multimedia coprocessor with 50Mvertices/s programmable SIMD vertex shader for mobile applications. ESSCIRC Ju-Ho Sohn, Jeong-Ho Woo, Ramchan Woo, Hoi-Jun Yoo
2005	J	`jnl`	Low-power 3D graphics processors for mobile terminals. IEEE Commun. Mag. Ju-Ho Sohn, Yong-Ha Park, Chi-Weon Yoon, Ramchan Woo, Se-Jeong Park, Hoi-Jun Yoo
2004	—	`conf`	3D graphics circuits for 3G multimedia terminals. SoC Ramchan Woo
2004	J	`jnl`	A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications. IEEE J. Solid State Circuits Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Hoi-Jun Yoo
2004	J	`jnl`	A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals. IEEE J. Solid State Circuits Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, Hoi-Jun Yoo
2004	—	`conf`	A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications. ASP-DAC Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, Hoi-Jun Yoo
2004	—	`conf`	A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications. Graphics Hardware Ju-Ho Sohn, Ramchan Woo, Hoi-Jun Yoo
2003	—	`conf`	A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimedia terminals. ESSCIRC Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Hoi-Jun Yoo
2002	J	`jnl`	A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip. IEEE J. Solid State Circuits Ramchan Woo, Chi-Weon Yoon, Jeonghoon Kook, Se-Joong Lee, Hoi-Jun Yoo
2002	J	`jnl`	A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth. IEEE J. Solid State Circuits Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kang-Min Lee, Tae-Hum Yang, Jin-Yong Jung, Hoi-Jun Yoo
2002	—	`conf`	Optimization of portable system architecture for real-time 3D graphics. ISCAS (1) Ju-Ho Sohn, Ramchan Woo, Hoi-Jun Yoo
2001	—	`conf`	A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator. ISCAS (5) Kangmin Lee, Chi Weon Yoon, Ramchan Woo, Jeong-Hun Kook, Ja-Il Koo, Tae-Sung Jung, Hoi-Jun Yoo
2001	J	`jnl`	An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications. IEEE J. Solid State Circuits Chi-Weon Yoon, Ramchan Woo, Jeengheon Kook, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yeo
2000	C	`conf`	A 670 ps, 64 bit dynamic low-power adder design. ISCAS Ramchan Woo, Se-Joong Lee, Hoi-Jun Yoo