Ramayya Kumar - RankMe

34 papers A* 1A 1B 1C 1Misc 2Journal 5Unranked 22

Year	Rank	Type	Title / Venue / Authors
1999	Misc	`conf`	Invited Talk: Practical Use of Formal Verification - Where are we? Where do we go? VLSI Design Ramayya Kumar
1998	J	`jnl`	A Practical Methodology for the Formal Verification of RISC Processors. Formal Methods Syst. Des. Sofiène Tahar, Ramayya Kumar
1997	—	`conf`	A constructive approach towards correctness of synthesis-application within retiming. ED&TC Dirk Eisenbiegler, Ramayya Kumar, Christian Blumenröhr
1996	B	`conf`	Formal Synthesis in Circuit Design - A Classification and Survey. FMCAD Ramayya Kumar, Christian Blumenröhr, Dirk Eisenbiegler, Detlef Schmid
1996	—	`conf`	Implementation Issues About the Embedding of Existing High Level Synthesis Algorithms in HOL. TPHOLs Dirk Eisenbiegler, Christian Blumenröhr, Ramayya Kumar
1995	—	`conf`	An Automata Theory Dedicated towards Formal Circuit Synthesis. TPHOLs Dirk Eisenbiegler, Ramayya Kumar
1995	J	`jnl`	Formal Specification and Verification Techniques for RISC Pipeline Conflicts. Comput. J. Sofiène Tahar, Ramayya Kumar
1995	Misc	`conf`	Formal synthesis of circuits with a simple handshake protocol. VLSI Design Ramayya Kumar, Thomas Kropf, Klaus Schneider
1995	—	`conf`	Formally embedding existing high level synthesis algorithms. CHARME Dirk Eisenbiegler, Ramayya Kumar
1995	—	`conf`	Generic design flows for project management in a framework environment. ED&TC Ewa Kwee-Christoph, Fridtjof Feldbusch, Ramayya Kumar, Arno Kunzmann
1994	—	`conf`	A Formal Framework for High Level Synthesis. TPCD Thomas Kropf, Klaus Schneider, Ramayya Kumar
1994	J	`jnl`	Accelerating Tableaux Proofs Using Compact Representations. Formal Methods Syst. Des. Klaus Schneider, Ramayya Kumar, Thomas Kropf
1994	—	`conf`	Automating Verification by Functional Abstraction at the System Level. TPHOLs Klaus Schneider, Ramayya Kumar, Thomas Kropf
1994	—	`conf`	Control Path Oriented Verification of Sequential Generic Circuits with Control and Data Path. EDAC-ETC-EUROASIC Klaus Schneider, Thomas Kropf, Ramayya Kumar
1994	—	`conf`	Formal verification of pipeline conflicts in RISC processors. EURO-DAC Ramayya Kumar, Sofiène Tahar
1994	—	`conf`	Implementational Issues for Verifying RISC-Pipeline Conflicts in HOL. TPHOLs Sofiène Tahar, Ramayya Kumar
1994	—	`ed.`	Theorem Provers in Circuit Design - Theory, Practice and Experience, Second International Conference, TPCD '94, Bad Herrenalb, Germany, September 26-28, 1994, Proceedings TPCD Ramayya Kumar, Thomas Kropf
1993	—	`conf`	A Functional Approach for Formalizing Regular Hardware Structures. HUG Dirk Eisenbiegler, Klaus Schneider, Ramayya Kumar
1993	—	`conf`	Alternative Proof Procedures for Finite-State Machines in Higher-Order Logic. HUG Klaus Schneider, Ramayya Kumar, Thomas Kropf
1993	—	`conf`	Eliminating Higher-Order Quantifiers to Obtain Decision Procedures for Hardware Verification. HUG Klaus Schneider, Ramayya Kumar, Thomas Kropf
1993	—	`conf`	Embedding Hardware Verification Within a Commercial Design Framework. CHARME Thomas Kropf, Ramayya Kumar, Klaus Schneider
1993	—	`conf`	Hardware-Verification using First Order BDDs. CHDL Klaus Schneider, Ramayya Kumar, Thomas Kropf
1993	—	`conf`	Implementing a Methodology for Formally Verifying RISC Processors in HOL. HUG Sofiène Tahar, Ramayya Kumar
1993	J	`jnl`	Structuring and Automating Hardware Proofs in a Higher-Order Theorem-Proving Environment. Formal Methods Syst. Des. Ramayya Kumar, Klaus Schneider, Thomas Kropf
1993	C	`conf`	Towards a Methodology for the Formal Hierarchical Verification. ICCD Sofiène Tahar, Ramayya Kumar
1992	—	`conf`	Efficient Representation and Computation of Tableau Proofs. TPHOLs Klaus Schneider, Ramayya Kumar, Thomas Kropf
1992	—	`conf`	Modelling Generic Hardware Structures by Abstract Datatypes. TPHOLs Klaus Schneider, Ramayya Kumar, Thomas Kropf
1992	A	`conf`	The FAUST - Prover. CADE Klaus Schneider, Ramayya Kumar, Thomas Kropf
1991	A*	`conf`	Automating Most Parts of Hardware Proofs in HOL. CAV Klaus Schneider, Ramayya Kumar, Thomas Kropf
1991	—	`conf`	First Steps Towards Automating Hardware Proofs in HOL. TPHOLs Ramayya Kumar, Thomas Kropf, Klaus Schneider
1991	—	`conf`	Integrating a First-Order Automatic Prover in the HOL Environment. TPHOLs Ramayya Kumar, Thomas Kropf, Klaus Schneider
1991	—	`conf`	Structure in Hardware Proofs: First Steps Towards Automation in a Higher-Order Environment. VLSI Klaus Schneider, Ramayya Kumar, Thomas Kropf
1991	—	`conf`	Verification of synthesized circuits at register transfer level with flow graphs. EURO-DAC Fridtjof Feldbusch, Ramayya Kumar
1989	J	`jnl`	CALLAS - ein System zur automatischen Synthese digitaler Schaltungen. Inform. Forsch. Entwickl. Thomas Wecker, Ramayya Kumar, Wolfgang Rosenstiel, Heinrich Krämer, Michael Neher