Ramachandra Achar

50 papers A* 1A 3Misc 3Journal 27Unranked 15
YearRankTypeTitle / Venue / Authors
2024 — conf
Recognition of Electronic Component Orientations from Hand-Drawn Circuit Schematics through a Two Stage Machine Learning System.
NewCAS
Anuj Mathur, Ramachandra Achar
2024 J jnl
cuTraNTT: A Novel Transposed Number Theoretic Transform Targeting Low Latency Homomorphic Encryption for IoT Applications.
IACR Cryptol. ePrint Arch.
Supriya Adhikary, Wai-Kong Lee, Angshuman Karmakar, Yongwoo Lee, Seong Oun Hwang, Ramachandra Achar
2023 — conf
PSIJ Transfer Function Response Prediction via NARNET and KBNNs.
NEWCAS
Ahsan Javaid, Ramachandra Achar
2022 J jnl
Algorithmic Advancements and a Comparative Investigation of Left and Right Looking Sparse LU Factorization on GPU Platform for Circuit Simulation.
IEEE Access
Wai-Kong Lee, Ramachandra Achar
2022 J jnl
DPCrypto: Acceleration of Post-Quantum Cryptography Using Dot-Product Instructions on GPUs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wai-Kong Lee, Hwajeong Seo, Seong Oun Hwang, Ramachandra Achar, Angshuman Karmakar, Jose Maria Bermudo Mera
2022 J jnl
Novel Observations and Physical Insights on PSIJ Behavior in CMOS Chain-of-Inverters.
IEEE Access
Muhammed Suhail Illikkal, Jai Narayan Tripathi, Vijender Kumar Sharma, Hitesh Shrimali, Ramachandra Achar
2021 J jnl
DPCrypto: Acceleration of Post-quantum Cryptographic Algorithms using Dot-Product Instruction on GPUs.
IACR Cryptol. ePrint Arch.
Wai-Kong Lee, Hwajeong Seo, Seong Oun Hwang, Angshuman Karmakar, Jose Maria Bermudo Mera, Ramachandra Achar
2021 J jnl
GPU-Accelerated Adaptive PCBSO Mode-Based Hybrid RLA for Sparse LU Factorization in Circuit Simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wai-Kong Lee, Ramachandra Achar
2020 — conf
A Comparative Study of MAGMA and cuBLAS Libraries for GPU based Vector Fitting.
LASCAS
Srinidhi Ganeshan, Naveen Kumar Elumalai, Ramachandra Achar
2020 J jnl
An energy efficient FPGA partial reconfiguration based micro-architectural technique for IoT applications.
Microprocess. Microsystems
Wei Pau Kiat, Kai Ming Mok, Wai-Kong Lee, Hock Guan Goh, Ramachandra Achar
2019 — conf
A Segmentation Algorithm for Capacitively Loaded Planar Resonant Structures.
LASCAS
Ihsan Erdin, Ramachandra Achar
2019 J jnl
A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers.
IEEE Access
Jai Narayan Tripathi, Muhammed Suhail Illikkal, Hitesh Shrimali, Ramachandra Achar
2018 J jnl
Dynamic GPU Parallel Sparse LU Factorization for Fast Circuit Simulation.
IEEE Trans. Very Large Scale Integr. Syst.
Wai-Kong Lee, Ramachandra Achar, Michel S. Nakhla
2018 J jnl
Fast Analysis of Time Interval Error in Current-Mode Drivers.
IEEE Trans. Very Large Scale Integr. Syst.
Jai Narayan Tripathi, Ramachandra Achar, Rakesh Malik
2017 J jnl
Parallel High-Order Envelope-Following Method for Fast Transient Analysis of Highly Oscillatory Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Mina A. Farhan, Michel S. Nakhla, Emad Gad, Ramachandra Achar
2014 J jnl
Addressing Partitioning Issues in Parallel Circuit Simulation.
IEEE Trans. Very Large Scale Integr. Syst.
Douglas Paul, Ramachandra Achar, Michel S. Nakhla, Natalie Nakhla
2013 — conf
Efficient parallel scheduler for circuit simulation exploiting binary link formulations.
LASCAS
Douglas Paul, Ramachandra Achar, Michel S. Nakhla, Natalie Nakhla
2012 J jnl
Structural Characterization and Efficient Implementation Techniques for $A$-Stable High-Order Integration Methods.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yinghong Zhou, Emad Gad, Michel S. Nakhla, Ramachandra Achar
2011 J jnl
Parallel and Scalable Transient Simulator for Power Grids via Waveform Relaxation (PTS-PWR).
IEEE Trans. Very Large Scale Integr. Syst.
Ramachandra Achar, Michel S. Nakhla, Harjot S. Dhindsa, Arvind R. Sridhar, Douglas Paul, Natalie Nakhla
2010 J jnl
Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nick Soveiko, Michel S. Nakhla, Ramachandra Achar
2009 J jnl
A-Stable and L-Stable High-Order Integration Methods for Solving Stiff Differential Equations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Emad Gad, Michel S. Nakhla, Ramachandra Achar, Yinghong Zhou
2009 J jnl
Passivity Compensation Algorithm for Method-of-Characteristics-Based Multiconductor Transmission Line Interconnect Macromodels.
IEEE Trans. Very Large Scale Integr. Syst.
Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub
2008 J jnl
A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub
2007 J jnl
Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Changzhong Chen, Emad Gad, Natalie Nakhla, Ramachandra Achar
2007 J jnl
Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels.
IEEE Trans. Very Large Scale Integr. Syst.
Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
2007 A conf
Sparse and passive reduction of massively coupled large multiport interconnects.
ICCAD
Natalie Nakhla, Michel S. Nakhla, Ramachandra Achar
2006 J jnl
A Projection-Based Reduction Approach to Computing Sensitivity of Steady-State Response of Nonlinear Circuits.
INFORMS J. Comput.
Praveen Pai, Emad Gad, Ramachandra Achar, Michel S. Nakhla, Roni Khazaka
2006 Misc conf
Circuit Compatible Macromodeling of High-Speed VLSI Modules Characterized by Scattering Parameters.
VLSI Design
Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
2006 Misc conf
Efficient and Accurate EMC Analysis of High-Frequency VLSI Subnetworks.
VLSI Design
Gurpreet Shinh, Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Ihsan Erdin
2005 — conf
Accurate and closed-form SPICE compatible passive macromodels for distributed interconnects with frequency dependent parameters.
ISCAS (6)
Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla
2005 — conf
Delay extraction based closed-form SPICE compatible passive macromodels for distributed transmission line interconnects.
ASP-DAC
Natalie Nakhla, Ramachandra Achar, Michel S. Nakhla, Anestis Dounavis
2005 J jnl
Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data.
IEEE Trans. Very Large Scale Integr. Syst.
Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
2005 — conf
On passivity enforcement for macromodels of S-parameter based tabulated subnetworks.
ISCAS (4)
Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
2005 J jnl
Passivity verification in delay-based macromodels of electrical interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap.
Emad Gad, Changzhong Chen, Michel S. Nakhla, Ramachandra Achar
2005 Misc conf
Projection Based Fast Passive Compact Macromodeling of High-Speed VLSI Circuits and Interconnects.
VLSI Design
Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
2004 — conf
Computing large-change sensitivity of periodic responses of nonlinear circuits using reduction techniques.
ISCAS (5)
Praveen Pai, Emad Gad, Ramachandra Achar, Roni Khazaka, Michel S. Nakhla
2004 — conf
Fast sensitivity analysis of transmission line networks.
ISCAS (5)
Natalie Nakhla, Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla
2003 — conf
Passive macromodeling of subnetworks characterized by measured data.
ISCAS (3)
Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla
2002 — conf
Passive closed-form time-domain macromodels for on-chip distributed RC interconnects.
CICC
Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla
2001 — conf
A general class of passive macromodels for efficient sensitivity analysis of high-speed distributed interconnects with nonlinear terminations.
ICECS
Anestis Dounavis, Ramachandra Achar, Michel S. Nakhla
2001 J jnl
Correction To "simulation of high-speed Interconnects".
Proc. IEEE
Ramachandra Achar, Michel S. Nakhla
2001 J jnl
Simulation of high-speed interconnects.
Proc. IEEE
Ramachandra Achar, Michel S. Nakhla
2000 A* conf
Passive model order reduction of multiport distributed interconnects.
DAC
Emad Gad, Anestis Dounavis, Michel S. Nakhla, Ramachandra Achar
2000 J jnl
Simulation of high-speed distributed interconnects using Krylov-space techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar
1999 — conf
Efficient simulation of on-chip RF components using model-reduction techniques.
ISCAS (2)
Ramachandra Achar, Michel S. Nakhla
1999 — ch.
Interconnect Modeling and Simulation.
The VLSI Handbook
Michel S. Nakhla, Ramachandra Achar
1999 — conf
Multi-point multi-port reduction of high-speed distributed interconnects using Krylov-space techniques.
ISCAS (6)
Pavan K. Gunupudi, Michel S. Nakhla, Ramachandra Achar
1998 J jnl
Full-wave analysis of high-speed interconnects using complex frequency hopping.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang
1996 A conf
An efficient approach for moment-matching simulation of linear subnetworks with measured or tabulated data.
ICCAD
Guowu Zheng, Qi-Jun Zhang, Michel S. Nakhla, Ramachandra Achar
1995 A conf
Addressing high frequency effects in VLSI interconnects with full wave model and CFH.
ICCAD
Ramachandra Achar, Michel S. Nakhla, Qi-Jun Zhang