Rama Sangireddy

25 papers B 2C 4Misc 5Journal 10Unranked 4
YearRankTypeTitle / Venue / Authors
2010 — conf
Application Specific Instruction Accelerator for Multistandard Viterbi and Turbo Decoding.
ICPP Workshops
Mangesh K. Kunchamwar, Durga P. Prasad, Pawan Hegde, Poras T. Balsara, Rama Sangireddy
2009 J jnl
Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors.
IEEE Trans. Parallel Distributed Syst.
Hui Wang, Rama Sangireddy, Sandeep Baldawa
2008 Misc conf
An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies.
VLSI Design
Terrell R. Bennett, Rama Sangireddy
2008 Misc conf
Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures.
VLSI Design
Hui Wang, Sandeep Baldawa, Rama Sangireddy
2008 J jnl
Operand-Load-Based Split Pipeline Architecture for High Clock Rate and Commensurable IPC.
IEEE Trans. Parallel Distributed Syst.
Rama Sangireddy, Jatan P. Shah
2008 J jnl
Streamlining long latency instructions for seamlessly combined out-of-order and in-order execution.
Microprocess. Microsystems
Hui Wang, Rama Sangireddy
2007 C conf
Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline Clustering.
ISCAS
Jatan P. Shah, Rama Sangireddy
2007 J jnl
Register port complexity reduction in wide-issue processors with selective instruction execution.
Microprocess. Microsystems
Rama Sangireddy
2007 J jnl
Scalable Reconfigurable Architectures for High-Performance Energy-Efficient Multimedia Processing.
Int. J. Comput. Their Appl.
Rama Sangireddy, Prabhu Rajamani
2006 C conf
Fast and low-power processor front-end with reduced rename logic circuit complexity.
ISCAS
Rama Sangireddy
2006 C conf
High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization.
IPCCC
Prabhu Rajamani, Jatan P. Shah, Vadhiraj Sankaranarayanan, Rama Sangireddy
2006 — conf
Instruction Format Based Selective Execution for Register Port Complexity Reduction in High-Performance Processors.
ITNG
Rama Sangireddy
2006 J jnl
On-Chip Adaptive Circuits for Fast Media Processing.
IEEE Trans. Circuits Syst. II Express Briefs
Rama Sangireddy, Arun K. Somani
2006 Misc conf
Performance Optimization with Scalable Reconfigurable Computing Systems.
VLSI Design
Rama Sangireddy, Prabhu Rajamani, Shwetha Gaddam
2006 J jnl
Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures.
IEEE Trans. Computers
Rama Sangireddy
2005 J jnl
Scalable, memory efficient, high-speed IP lookup algorithms.
IEEE/ACM Trans. Netw.
Rama Sangireddy, Natsuhiko Futamura, Srinivas Aluru, Arun K. Somani
2004 C conf
Exploiting Quiescent States in Register Lifetime.
ICCD
Rama Sangireddy, Arun K. Somani
2004 J jnl
Low-Power High-Performance Reconfigurable Computing Cache Architectures.
IEEE Trans. Computers
Rama Sangireddy, Huesung Kim, Arun K. Somani
2004 — conf
Register Organization for Enhanced On-Chip Parallelism.
ASAP
Rama Sangireddy
2003 — conf
Application-Specific Computing with Adaptive Register File Architectures.
ASAP
Rama Sangireddy, Arun K. Somani
2003 J jnl
High-speed IP routing with binary decision diagrams based hardware address lookup engine.
IEEE J. Sel. Areas Commun.
Rama Sangireddy, Arun K. Somani
2003 B conf
Scalable, memory efficient, high-speed lookup and update algorithms for IP routing.
ICCCN
Natsuhiko Futamura, Rama Sangireddy, Srinivas Aluru, Arun K. Somani
2003 Misc conf
Timing Issues of Operating Mode Switch in High Performance Reconfigurable Architectures.
HiPC
Rama Sangireddy, Huesung Kim, Arun K. Somani
2002 Misc conf
Low-Power High-Performance Adaptive Computing Architectures for Multimedia Processing.
HiPC
Rama Sangireddy, Huesung Kim, Arun K. Somani
2001 B conf
Binary decision diagrams for efficient hardware implementation of fast IP routing lookups.
ICCCN
Rama Sangireddy, Arun K. Somani