Rama Muni Reddy Yanamala

20 papers Journal 17Unranked 3
YearRankTypeTitle / Venue / Authors
2026 J jnl
Elevating efficiency: Field-Programmable Gate Array Powered Acceleration of MobileNet V1 with patchwise innovation, double buffering, and Singular Value Decomposition Optimization.
Eng. Appl. Artif. Intell.
Rama Muni Reddy Yanamala, Muralidhar Pullakandam, Rayappa David Amar Raj
2026 J jnl
FPGA-Powered Solar Photovoltaic Module Defect Classification: Patch-Wise Reusable Convolutional Neural Network Intellectual Properties for High-Speed Edge Processing.
J. Comput. Inf. Sci. Eng.
Ghanashyam Vinod, Rama Muni Reddy Yanamala, Rayappa David Amar Raj, T. Subeesh, V. Anandkumar, Rouzbeh Nazari, Manasa V, Archana Pallakonda
2026 J jnl
Formalized dual-stream hybrid convolutional neural network for efficient multi-scale tampering detection via feature-driven fusion.
Eng. Appl. Artif. Intell.
Archana Pallakonda, Rama Muni Reddy Yanamala, Enku Sai Mohith, Rayappa David Amar Raj
2026 J jnl
Hierarchical mobile-dense convolutional architecture for tampered image detection using focal optimization with quantized edge TPU deployment.
Comput. Electr. Eng.
Badam Shanmukha Venkata Vinayak, Rama Muni Reddy Yanamala, Rayappa David Amar Raj, Archana Pallakonda
2025 J jnl
A Holistic Framework for Cyber Attack Detection, Classification, and Security Enhancement of DNP3 Protocol in Smart Grids.
IEEE Access
Jyothsna Vaasudevan, Harish Manukonda, Archana Pallakonda, Rayappa David Amar Raj, Rama Muni Reddy Yanamala, Rouzbeh Nazari, K. Krishna Prakasha
2025 — conf
A Neural Framework For Handwritten Calendar Parsing and Semantic Content Categorization.
ICYRIME
Antoni Gagliard, Rayappa David Amar Raj, Rama Muni Reddy Yanamala
2025 J jnl
A Unified Cybersecurity Framework for Smart Grids Against Data Integrity Attacks Using Ensemble Learning and Hybrid Encryption.
IEEE Access
Archana Pallakonda, K. Ravishanmugam, Rayappa David Amar Raj, Sharvesh Sivagnanam, Rama Muni Reddy Yanamala, K. Krishna Prakasha
2025 J jnl
FPGA-Accelerated Sparse Subset Segmentation Using ADMM for High-Resolution Imagery.
IEEE Access
Rupali Karthikeyan, Deep Amit Lodaya, Rama Muni Reddy Yanamala, Rayappa David Amar Raj, K. Krishna Prakasha, T. Subeesh, V. Anandkumar, Archana Pallakonda
2025 J jnl
FPGA-accelerated hybrid CNN-LSTM system for efficient EEG-based drowsiness recognition.
J. Supercomput.
Rama Muni Reddy Yanamala, Muralidhar Pullakandam
2025 J jnl
Lightweight End-to-End Patch-Based Self-Attention Network for Robust Image Forgery Detection.
IEEE Access
Police Aryan, Rama Muni Reddy Yanamala, Archana Pallakonda, Rayappa David Amar Raj, K. Krishna Prakasha
2025 J jnl
Lightweight spatial attention pyramid network-based image forgery detection optimized for real-time edge TPU deployment.
Comput. Electr. Eng.
Baby Sree Gangarapu, Rama Muni Reddy Yanamala, Archana Pallakonda, Hindupur Raghavender Vardhan, Rayappa David Amar Raj
2025 J jnl
Secure and Resilient Cyberattack Detection in ICS Networks: Hybrid Encryption, Protocol Hardening, and Threat Hunting on ELECTRA Modbus Traffic.
IEEE Access
Archana Pallakonda, S. Sanjay Kumar, Rayappa David Amar Raj, Rama Muni Reddy Yanamala, K. Krishna Prakasha
2025 J jnl
Smart Grid Intrusion Detection for IEC 60870-5-104 With Feature Optimization, Privacy Protection, and Honeypot-Firewall Integration.
IEEE Access
Pedamallu Sai Mrudula, Rayappa David Amar Raj, Archana Pallakonda, Rama Muni Reddy Yanamala, K. Krishna Prakasha, V. Anand Kumar
2025 J jnl
TL-Efficient-SE: A Transfer Learning-Based Attention-Enhanced Model for Fingerprint Liveness Detection Across Multi-Sensor Spoof Attacks.
Mach. Learn. Knowl. Extr.
Archana Pallakonda, Rayappa David Amar Raj, Rama Muni Reddy Yanamala, Christian Napoli, Cristian Randieri
2025 J jnl
YOLOv8n-GBE: A Hybrid YOLOv8n Model With Ghost Convolutions and BiFPN-ECA Attention for Solar PV Defect Localization.
IEEE Access
Likitha Reddy Yeddula, Archana Pallakonda, Rayappa David Amar Raj, Rama Muni Reddy Yanamala, K. Krishna Prakasha, Mallempati Sunil Kumar
2024 J jnl
Empowering edge devices: FPGA-based 16-bit fixed-point accelerator with SVD for CNN on 32-bit memory-limited systems.
Int. J. Circuit Theory Appl.
Rama Muni Reddy Yanamala, Muralidhar Pullakandam
2024 J jnl
High-Speed Power Allocation in NOMA System Using FPGA-Based DNN.
J. Circuits Syst. Comput.
Rama Muni Reddy Yanamala, Muralidhar Pullakandam
2023 J jnl
A high-speed reusable quantized hardware accelerator design for CNN on constrained edge device.
Des. Autom. Embed. Syst.
Rama Muni Reddy Yanamala, Muralidhar Pullakandam
2023 — conf
Pneumonia Detection Using Transfer Learning And Hardware Implementation in Edge TPU.
ICCCNT
Sujay Kumar Mandal, Muralidhar Pullakandam, Rama Muni Reddy Yanamala
2022 — conf
An Efficient Configurable Hardware Accelerator Design for CNN on Low Memory 32-Bit Edge Device.
iSES
Rama Muni Reddy Yanamala, Muralidhar Pullakandam