Ram Krishnamurthy

97 papers A* 3A 9C 8Misc 3Journal 15Unranked 58

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	30.9 A 147TOPS/W, 250TOPS/mm ISSCC Amit Agarwal, Steven K. Hsu, Mark A. Anders, Arnab Raha, Deepak A. Mathaikutty, Ram Krishnamurthy
2025	—	`conf`	A 93.9% Peak Efficiency 3V-to-40V-Input GaN-based DC-DC Converter with Unified Reliability and Efficiency Adaptive Control. CICC Zhaoqing Wang, Yichen Xu, Suhwan Kim, Nachiket V. Desai, Minxiang Gong, Ram Krishnamurthy, Xin Zhang, Mingoo Seok
2025	J	`jnl`	Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency. IEEE Solid State Circuits Lett. Yichen Xu, Zhaoqing Wang, Rentao Wan, Suhwan Kim, Minxiang Gong, Ram Krishnamurthy, Xin Zhang, Mingoo Seok
2025	J	`jnl`	T-REX: A 68-567 μs/token, 0.41-3.95 μJ/token Transformer Accelerator with Reduced External Memory Access and Enhanced Hardware Utilization in 16nm FinFET. CoRR Seunghyun Moon, Mao Li, Gregory K. Chen, Phil C. Knag, Ram Krishnamurthy, Mingoo Seok
2022	—	`conf`	2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators. VLSI Technology and Circuits Steven Hsu, Amit Agarwal, Mark A. Anders, Arnab Raha, Raymond Sung, Deepak Mathaikutty, Ram Krishnamurthy, James W. Tschanz, Vivek De
2022	—	`conf`	On-Chip High-Resolution Timing Characterization Circuits for Memory IPs. ESSCIRC Amit Agarwal, Steven Hsu, Mark A. Anders, Gunjan Pandya, Ram Krishnamurthy, James W. Tschanz, Vivek De
2021	J	`jnl`	Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. IEEE Trans. Very Large Scale Integr. Syst. Sriram R. Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James W. Tschanz, Vivek De, Chris H. Kim
2020	—	`conf`	25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. ISSCC Amit Agarwal, Steven Hsu, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De
2020	—	`conf`	A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. VLSI Circuits Monodeep Kar, Amit Agarwal, Steven Hsu, David Moloney, Gregory K. Chen, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Mark A. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, Ram Krishnamurthy, Vivek De
2020	—	`conf`	Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. VLSI Circuits Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De
2019	—	`conf`	A 1.4GHz 20.5Gbps GZIP decompression accelerator in 14nm CMOS featuring dual-path out-of-order speculative Huffman decoder and multi-write enabled register file array. VLSI Circuits Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew
2019	—	`conf`	A 220-900mV 179Mcode/s 36pJ/code Canonical Huffman Encoder for DEFLATE Compression in 14nm CMOS. CICC Sudhir Satpathy, Vikram B. Suresh, Raghavan Kumar, Vinodh Gopal, James Guilford, Kirk Yap, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew
2019	—	`conf`	A 225-950mV 1.5Tbps/W Whirlpool Hashing Accelerator for Secure Automotive Platforms in 14nm CMOS. CICC Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Sanu Mathew
2019	—	`conf`	A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm CMOS Featuring Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking. VLSI Circuits Vikram B. Suresh, Sudhir Satpathy, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De, Sanu Mathew
2019	—	`conf`	A 4900×m VLSI Circuits Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew
2019	—	`conf`	A 54% Power-Saving Static Fully-Interruptible Single-Phase-Clocked Shared-Keeper Flip-Flop in 14nm CMOS. A-SSCC Amit Agarwal, Steven Hsu, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De
2019	—	`conf`	A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power AOI Clocked Circuits in 14nm CMOS. VLSI Circuits Steven Hsu, Amit Agarwal, Monodeep Kar, Mark A. Anders, Himanshu Kaul, Raghavan Kumar, Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Ram Krishnamurthy, Vivek De
2019	A	`conf`	Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. FPGA Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Aravind Dasu
2019	C	`conf`	Optimized Fused Floating-Point Many-Term Dot-Product Hardware for Machine Learning Accelerators. ARITH Himanshu Kaul, Mark A. Anders, Sanu Mathew, Seongjong Kim, Ram Krishnamurthy
2019	Misc	`conf`	Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. FCCM Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr, Aravind Dasu
2018	—	`conf`	2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS. VLSI Circuits Mark A. Anders, Himanshu Kaul, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	—	`conf`	220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(2 VLSI Circuits Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	—	`conf`	A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS. ESSCIRC Vikram B. Suresh, Sudhir Satpathy, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	—	`conf`	A 280mV 3.1pJ/code Huffman Decoder for DEFLATE Decompression Featuring Opportunistic Code Skip and 3-way Symbol Generation in 14nm Tri-gate CMOS. A-SSCC Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Vinodh Gopal, James Guilford, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	—	`conf`	An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms. VLSI Circuits Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De
2018	—	`conf`	Ultra-Lightweight 548-1080 Gate 166Gbps/W-12.6Tbps/W SIMON 32/64 Cipher Accelerators for IoT in 14nm Tri-gate CMOS. A-SSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2018	A	`conf`	Ultra-low energy circuit building blocks for security technologies. DATE Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram Krishnamurthy
2017	J	`jnl`	Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations. CoRR Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo
2017	—	`conf`	Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. BioCAS Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo
2017	A	`conf`	Invited paper: Ultra-low energy security circuit primitives for IoT platforms. ISLPED Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Ram Krishnamurthy
2017	J	`jnl`	Near Threshold Voltage (NTV) Computing: Computing in the Dark Silicon Era. IEEE Des. Test Vivek De, Sriram R. Vangal, Ram Krishnamurthy
2016	—	`conf`	14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Gregory K. Chen, Sudhir Satpathy, Steven Hsu, Amit Agarwal, Ram Krishnamurthy
2016	—	`conf`	250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS. VLSI Circuits Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy
2016	—	`conf`	A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS. A-SSCC Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Gregory K. Chen, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De
2016	—	`conf`	A 350mV-900mV 2.1GHz 0.011mm VLSI Circuits Amit Agarwal, Steven Hsu, Mark A. Anders, Sanu Mathew, Gregory K. Chen, Himanshu Kaul, Sudhir Satpathy, Ram Krishnamurthy
2016	—	`conf`	A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. VLSI Circuits Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De
2016	C	`conf`	Ultra-low energy security circuits for IoT applications. ICCD Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Ram Krishnamurthy
2015	J	`jnl`	340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy
2015	J	`jnl`	A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Borkar
2015	—	`conf`	μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS. ESSCIRC Sanu Mathew, David Johnston, Paul Newman, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2014	—	`conf`	13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS. ESSCIRC Sudhir Satpathy, Sanu Mathew, Jiangtao Li, Patrick Koeberl, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2014	—	`conf`	340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(2 VLSIC Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Himanshu Kaul, Mark A. Anders, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy
2013	C	`conf`	Split-Path Fused Floating Point Multiply Accumulate (FPMAC). IEEE Symposium on Computer Arithmetic Suresh Srinivasan, Ketan Bhudiya, Rajaraman Ramanarayanan, P. Sahit Babu, Tiju Jacob, Sanu Mathew, Ram Krishnamurthy, Vasantha Erraguntla
2012	J	`jnl`	2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors. IEEE J. Solid State Circuits Sanu Mathew, Suresh Srinivasan, Mark A. Anders, Himanshu Kaul, Steven Hsu, Farhana Sheikh, Amit Agarwal, Sudhir Satpathy, Ram Krishnamurthy
2012	—	`conf`	A 1.45GHz 52-to-162GFLOPS/W variable-precision floating-point fused multiply-add unit with certainty tracking in 32nm CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
2012	—	`conf`	A 2.05GVertices/s 151mW lighting accelerator for 3D graphics vertex and pixel shading in 32nm CMOS. ISSCC Farhana Sheikh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2012	—	`conf`	A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS. VLSIC Steven Hsu, Amit Agarwal, Mark A. Anders, Himanshu Kaul, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
2012	—	`conf`	A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS. ESSCIRC Amit Agarwal, Steven Hsu, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy
2012	—	`conf`	A 280mV-to-1.1V 256b reconfigurable SIMD vector permutation engine with 2-dimensional shuffle in 22nm CMOS. ISSCC Steven Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy
2012	A*	`conf`	Near-threshold voltage (NTV) design: opportunities and challenges. DAC Himanshu Kaul, Mark A. Anders, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2011	J	`jnl`	53 Gbps Native GF(2 IEEE J. Solid State Circuits Sanu Mathew, Farhana Sheikh, Michael E. Kounavis, Shay Gueron, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Ram Krishnamurthy
2011	—	`conf`	A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS. ESSCIRC Amit Agarwal, Steven Hsu, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Ram Krishnamurthy
2011	J	`jnl`	A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect. IEEE Trans. Very Large Scale Integr. Syst. Jae-sun Seo, Himanshu Kaul, Ram Krishnamurthy, Dennis Sylvester, David T. Blaauw
2011	A*	`conf`	High-performance energy-efficient encryption in the sub-45nm CMOS Era. DAC Ram Krishnamurthy, Sanu Mathew, Farhana Sheikh
2011	—	`ed.`	Reconfigurable Computing: Architectures, Tools and Applications - 7th International Symposium, ARC 2011, Belfast, UK, March 23-25, 2011. Proceedings ARC Andreas Koch, Ram Krishnamurthy, John McAllister, Roger F. Woods, Tarek A. El-Ghazawi
2010	—	`conf`	18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS. ESSCIRC Rajaraman Ramanarayanan, Sanu Mathew, Farhana Sheikh, Suresh Srinivasan, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Vasantha Erraguntla, Ram Krishnamurthy
2010	—	`conf`	3GHz, 74mW 2-level Karatsuba 64b Galois field multiplier for public-key encryption acceleration in 45nm CMOS. ESSCIRC Sanu Mathew, Michael E. Kounavis, Farhana Sheikh, Steven Hsu, Amit Agarwal, Himanshu Kaul, Mark A. Anders, Frank L. Berry, Ram Krishnamurthy
2010	J	`jnl`	A 300 mV 494GOPS/W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS. IEEE J. Solid State Circuits Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2010	—	`conf`	A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS. ISSCC Amit Agarwal, Sanu Mathew, Steven Hsu, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar
2010	—	`conf`	A 4.1Tb/s bisection-bandwidth 560Gb/s/W streaming circuit-switched 8×8 mesh network-on-chip in 45nm CMOS. ISSCC Mark A. Anders, Himanshu Kaul, Steven Hsu, Amit Agarwal, Sanu Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
2010	—	`conf`	High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors. ARC Ram Krishnamurthy
2010	—	`conf`	Signal and power integrity for SoCs. ISSCC Don Draper, Fabio Campi, Ram Krishnamurthy, Takashi Miyamori, Shannon Morton, Willy Sansen, Vladimir Stojanovic, John T. Stonick
2009	—	`conf`	A 300mV 494GOPS/W reconfigurable dual-supply 4-Way SIMD vector processing accelerator in 45nm CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2009	Misc	`conf`	A 4Gbps 0.57pJ/bit Process-Voltage-Temperature Variation Tolerant All-Digital True Random Number Generator in 45nm CMOS. VLSI Design Suresh Srinivasan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy
2008	Misc	`conf`	A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores. VLSI Design Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron
2008	—	`conf`	A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS. ESSCIRC Mark A. Anders, Himanshu Kaul, Martin Hansson, Ram Krishnamurthy, Shekhar Borkar
2008	—	`conf`	A 320mV 56μW 411GOPS/Watt Ultra-Low Voltage Motion Estimation Accelerator in 65nm CMOS. ISSCC Himanshu Kaul, Mark A. Anders, Sanu Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Shekhar Borkar
2008	C	`conf`	A robust alternate repeater technique for high performance busses in the multi-core era. ISCAS Himanshu Kaul, Jae-sun Seo, Mark A. Anders, Dennis Sylvester, Ram Krishnamurthy
2007	—	`conf`	A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS. ISSCC Mark A. Anders, Sanu Mathew, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
2007	—	`conf`	A 2.4GHz 256/1024-bit Encryption Accelerator reconfigurable Montgomery multiplier in 90nm CMOS. SoCC Sanu Mathew, David Money Harris, Mark A. Anders, Steven Hsu, Ram Krishnamurthy
2007	A	`conf`	A robust edge encoding technique for energy-efficient multi-cycle interconnect. ISLPED Jae-sun Seo, Dennis Sylvester, David T. Blaauw, Himanshu Kaul, Ram Krishnamurthy
2007	—	`conf`	SE4 Automotive Signal Processing Technologies. ISSCC Toru Shimizu, Ram Krishnamurthy
2006	—	`conf`	A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core. ISSCC Sapumal B. Wijeratne, Nanda Siddaiah, Sanu Mathew, Mark A. Anders, Ram Krishnamurthy, Jeremy Anderson, Seung Hwang, Matthew Ernest, Mark D. Nardin
2006	—	`conf`	A Low-swing Signaling Circuit Technique for 65nm On-chip Interconnects. SoCC Vishak Venkatraman, Mark A. Anders, Himanshu Kaul, Wayne P. Burleson, Ram Krishnamurthy
2006	J	`jnl`	A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits. IEEE Trans. Very Large Scale Integr. Syst. Chris H. Kim, Kaushik Roy, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
2006	—	`conf`	An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS. ISSCC Steven K. Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Ram Krishnamurthy, Shekhar Borkar
2006	—	`conf`	High-performance energy-efficient memory circuit technologies for sub-45nm technologies. SoCC Amit Agarwal, Ram Krishnamurthy
2005	—	`conf`	A 2GHz 13.6mW 12 × 9b multiplier for energy efficient FFT accelerators. ESSCIRC Steven Hsu, Vishak Venkatraman, Sanu Mathew, Himanshu Kaul, Mark A. Anders, Saurabh Dighe, Wayne P. Burleson, Ram Krishnamurthy
2005	A	`conf`	An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS. ISLPED Steven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Borkar
2005	C	`conf`	An Improved Unified Scalable Radix-2 Montgomery Multiplier. IEEE Symposium on Computer Arithmetic David Money Harris, Ram Krishnamurthy, Mark A. Anders, Sanu Mathew, Steven Hsu
2005	J	`jnl`	Comparison of high-performance VLSI adders in the energy-delay space. IEEE Trans. Very Large Scale Integr. Syst. Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy
2005	J	`jnl`	Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses. IEEE Trans. Very Large Scale Integr. Syst. Himanshu Kaul, Dennis Sylvester, Mark A. Anders, Ram Krishnamurthy
2005	J	`jnl`	Designing leakage tolerant, low power wide-OR dominos for sub-130nm CMOS technologies. Microelectron. J. Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
2005	C	`conf`	Self Calibrating Circuit Design for Variation Tolerant VLSI Systems. IOLTS Chris H. Kim, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar, Kaushik Roy
2004	A	`conf`	A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies. ISLPED Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
2004	—	`conf`	Leakage Control Techniques for Designing Robust, Low Power Wide-OR Domino Logic for sub-130 nm CMOS Technologies. ISQED Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
2004	A	`conf`	Spatial encoding circuit techniques for peak power reduction of on-chip high-performance buses. ISLPED Himanshu Kaul, Dennis Sylvester, Mark A. Anders, Ram Krishnamurthy
2003	—	`conf`	Bitline leakage equalization for sub-100nm caches. ESSCIRC Atila Alvandpour, Dinesh Somasekhar, Ram Krishnamurthy, Vivek De, Shekhar Borkar, Christer Svensson
2003	A	`conf`	Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. ISLPED Bhaskar Chatterjee, Manoj Sachdev, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar
2003	C	`conf`	Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders. IEEE Symposium on Computer Arithmetic Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy
2003	—	`conf`	Low voltage sensing techniques and secondary design issues for sub-90nm caches. ESSCIRC Manoj Sinha, Steven Hsu, Atila Alvandpour, Wayne P. Burleson, Ram Krishnamurthy, Shekhar Borkar
2003	C	`conf`	Tutorial: Design of Power Efficient VLSI Arithmetic: Speed and Power Trade-Offs. IEEE Symposium on Computer Arithmetic Vojin G. Oklobdzija, Ram Krishnamurthy
2002	—	`conf`	A burn-in tolerant dynamic circuit technique. CICC Atila Alvandpour, Ram Krishnamurthy, Shekhar Borkar, A. Rahman, Clair Webb
2002	A*	`conf`	Dynamic addressing memory arrays with physical locality. MICRO Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai
2001	A	`conf`	A low-leakage dynamic multi-ported register file in 0.13mm CMOS. ISLPED Atila Alvandpour, Ram Krishnamurthy, Krishnamurthy Soumyanath, Shekhar Borkar
2001	—	`conf`	Leakage control and tolerance challenges for sub-0.1µm microprocessor circuits. ACM Great Lakes Symposium on VLSI Ram Krishnamurthy, Mark A. Anders, Krishnamurthy Soumyanath, Shekhar Borkar
1998	—	`conf`	A low-power 16-bit multiplier-accumulator using series-regulated mixed swing techniques. CICC Ram Krishnamurthy, Herman Schmit, L. Richard Carley