Ralph Wittig - RankMe

17 papers A* 1A 1B 1Misc 1Journal 5Unranked 8

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Parallelization Strategies for DLRM Embedding Bag Operator on AMD CPUs. IEEE Micro Krishnakumar Nair, Avinash-Chandra Pandey, Siddappa Karabannavar, Meena Arunachalam, John Kalamatianos, Varun Agrawal, Saurabh Gupta, Ashish Sirasao, Elliott Delaye, Steven K. Reinhardt, Rajesh Vivekanandham, Ralph Wittig, Vinod Kathail, Padmini Gopalakrishnan, Satyaprakash Pareek, Rishabh Jain, Mahmut Taylan Kandemir, Jun-Liang Lin, Gulsum Gudukbay Akbulut, Chita R. Das
2023	J	`jnl`	Microscaling Data Formats for Deep Learning. CoRR Bita Darvish Rouhani, Ritchie Zhao, Ankit More, Mathew Hall, Alireza Khodamoradi, Summer Deng, Dhruv Choudhary, Marius Cornea, Eric Dellinger, Kristof Denolf, Dusan Stosic, Venmugil Elango, Maximilian Golub, Alexander Heinecke, Phil James-Roxby, Dharmesh Jani, Gaurav Kolhe, Martin Langhammer, Ada Li, Levi Melnick, Maral Mesmakhosroshahi, Andres Rodriguez, Michael Schulte, Rasoul Shafipour, Lei Shao, Michael Y. Siu, Pradeep Dubey, Paulius Micikevicius, Maxim Naumov, Colin Verilli, Ralph Wittig, Doug Burger, Eric S. Chung
2020	—	`conf`	Xilinx Versal™ Premium. Hot Chips Symposium Martin Voogel, Yohan Frans, Matt Ouellette, Jason Coppens, Sagheer Ahmad, Jaideep Dastidar, Ehab Mohsen, Faisal Dada, Mike Thompson, Ralph Wittig, Trevor Bauer, Gaurav Singh
2019	—	`conf`	Xilinx First 7nm Device: Versal AI Core (VC1902). Hot Chips Symposium Sagheer Ahmad, Sridhar Subramanian, Vamsi Boppana, Shankar Lakka, Fu-Hing Ho, Tomai Knopp, Juanjo Noguera, Gaurav Singh, Ralph Wittig
2016	J	`jnl`	A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform. IEEE Micro Sagheer Ahmad, Vamsi Boppana, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig
2015	—	`conf`	OpenCL library of stream memory components targeting FPGAs. FPT Jasmina Vasiljevic, Ralph Wittig, Paul Schumacher, Jeff Fifield, Fernando Martinez-Vallina, Henry Styles, Paul Chow
2015	—	`conf`	UltraScale+ MPSoC and FPGA families. Hot Chips Symposium Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig
2011	—	`conf`	Xilinx Zynq-7000 EPP: An extensible processing platform family. Hot Chips Symposium Vidya Rajagopalan, Vamsi Boppana, Sandeep Dutta, Brad Taylor, Ralph Wittig
2010	—	`conf`	28nm generation programmable families. Hot Chips Symposium Brad Taylor, Ralph Wittig
2010	J	`jnl`	Guest Editors' Introduction: Hot Chips 21. IEEE Micro Krste Asanovic, Ralph Wittig
2010	J	`jnl`	MPI as a Programming Model for High-Performance Reconfigurable Computers. ACM Trans. Reconfigurable Technol. Syst. Manuel Saldaña, Arun Patel, Christopher A. Madill, Daniel Nunes, Danyao Wang, Paul Chow, Ralph Wittig, Henry Styles, Andrew Putnam
2009	A	`conf`	Performance and power of cache-based reconfigurable computing. FPGA Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig
2009	A*	`conf`	Performance and power of cache-based reconfigurable computing. ISCA Andrew Putnam, Susan J. Eggers, Dave Bennett, Eric Dellinger, Jeff Mason, Henry Styles, Prasanna Sundararajan, Ralph Wittig
2008	—	`conf`	Evaluating FPGAs for floating-point performance. HPRCTA@SC Dave Strenski, Jim Simkins, Richard Walke, Ralph Wittig
2008	—	`conf`	MPI as an abstraction for software-hardware interaction for HPRCs. HPRCTA@SC Manuel Saldaña, Arun Patel, Christopher A. Madill, Daniel Nunes, Danyao Wang, Henry Styles, Andrew Putnam, Ralph Wittig, Paul Chow
1998	B	`conf`	Generating Layouts for Self-implementing Modules. FPL James Hwang, Cameron Patterson, S. Mohan, Eric Dellinger, Sujoy Mitra, Ralph Wittig
1996	Misc	`conf`	OneChip: an FPGA processor with reconfigurable logic. FCCM Ralph Wittig, Paul Chow