Ralph K. Cavin III

52 papers A* 4C 2Journal 37Unranked 9
YearRankTypeTitle / Venue / Authors
2018 J jnl
Nurturing the Growth of a National Infrastructure in Emerging Technologies.
Proc. IEEE
Rafic Z. Makki, Victor V. Zhirnov, Ralph K. Cavin III, Sami Issa, Marco Iansiti
2012 J jnl
Prolog to the Section on Science and Engineering Beyond Moore's Law.
Proc. IEEE
Ralph K. Cavin III, Paolo Lugli, Victor V. Zhirnov
2012 J jnl
Science and Engineering Beyond Moore's Law.
Proc. IEEE
Ralph K. Cavin III, Paolo Lugli, Victor V. Zhirnov
2010 J jnl
Device and Architecture Outlook for Beyond CMOS Switches.
Proc. IEEE
Kerry Bernstein, Ralph K. Cavin III, Wolfgang Porod, Alan C. Seabaugh, Jeff Welser
2010 J jnl
Memory Devices: Energy-Space-Time Tradeoffs.
Proc. IEEE
Victor V. Zhirnov, Ralph K. Cavin III, Stephan Menzel, Eike Linn, Sebastian Schmelzer, Dennis Bräuhaus, Christina Schindler, Rainer Waser
2010 J jnl
Nanoelectronics Research for Beyond CMOS Information Processing.
Proc. IEEE
George Bourianoff, Michel Brillouët, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida
2010 J jnl
Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps.
Proc. IEEE
Michel Brillouët, George Bourianoff, Ralph K. Cavin III, Toshiro Hiramoto, James A. Hutchby, Adrian M. Ionescu, Ken Uchida
2009 — conf
Scaling beyond CMOS: Turing-Heisenberg Rapproachment.
ESSCIRC
Victor V. Zhirnov, Ralph K. Cavin III
2008 J jnl
An Assessment of Integrated Digital Cellular Automata Architectures.
Computer
Victor V. Zhirnov, Ralph K. Cavin III, Greg Leeming, Kosmas Galatsis
2008 J jnl
Boolean Logic and Alternative Information-Processing Devices.
Computer
George Bourianoff, Joe E. Brewer, Ralph K. Cavin III, James A. Hutchby, Victor V. Zhirnov
2008 J jnl
Emerging Nanoscale Memory and Logic Devices: A Critical Assessment.
Computer
James A. Hutchby, Ralph K. Cavin III, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff
2008 J jnl
Emerging Research Architectures.
Computer
Ralph K. Cavin III, James A. Hutchby, Victor V. Zhirnov, Joe E. Brewer, George Bourianoff
2008 — conf
The Viability of Cellular Automata Architectures for General Purpose Computing.
ERSA
Victor V. Zhirnov, Greg Leeming, Kosmas Galatsis, Ralph K. Cavin III
2006 J jnl
A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling.
IEEE J. Solid State Circuits
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards
2005 — conf
Future devices for information processing.
ESSCIRC
Ralph K. Cavin III, Victor V. Zhirnov
2004 J jnl
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability.
IEEE Trans. Very Large Scale Integr. Syst.
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III, Dale Edwards
2003 J jnl
A semiconductor industry perspective on future directions in ECE education.
IEEE Trans. Educ.
Ralph K. Cavin III, William H. Joyner Jr., Virginia C. Wiggins
2003 — conf
Accurate delay model and experimental verification for current/voltage mode on-chip interconnects.
ISCAS (5)
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
2003 J jnl
Current-mode signaling in deep submicrometer global interconnects.
IEEE Trans. Very Large Scale Integr. Syst.
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
2003 J jnl
Limits to binary logic switch scaling - a gedanken model.
Proc. IEEE
Victor V. Zhirnov, Ralph K. Cavin III, James A. Hutchby, George Bourianoff
2003 A* conf
Low-power design methodology for an on-chip bus with adaptive bandwidth capability.
DAC
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
2002 — conf
Delay and power model for current-mode signaling in deep submicron global interconnects.
CICC
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
2000 J jnl
Integrated parametric timing optimization of digital systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III
1997 J jnl
A CMOS high-speed data recovery circuit using the matched delay sampling technique.
IEEE J. Solid State Circuits
Jin-Ku Kang, Wentai Liu, Ralph K. Cavin III
1997 J jnl
Clocking Optimization and Distribution in Digital Systems with Scheduled Skews.
J. VLSI Signal Process.
Hong-Yean Hsieh, Wentai Liu, Paul D. Franzon, Ralph K. Cavin III
1997 J jnl
The delay vernier pattern generation technique.
IEEE J. Solid State Circuits
Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III
1995 — conf
A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.
ARVLSI
Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III
1995 C conf
Concurrent timing optimization of latch-based digital systems.
ICCD
Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III, C. Thomas Gray
1995 C conf
High Speed, Fine Resolution Pattern Generation Using the Matched Delay Technique.
ISCAS
Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III
1994 J jnl
A 250-MHz wave pipelined adder in 2-μm CMOS.
IEEE J. Solid State Circuits
Wentai Liu, C. Thomas Gray, David Fan, William J. Farlow, Thomas A. Hughes, Ralph K. Cavin III
1994 J jnl
A sampling technique and its CMOS implementation with 1 Gb/s bandwidth and 25 ps resolution.
IEEE J. Solid State Circuits
C. Thomas Gray, Wentai Liu, Wilhelmus A. M. Van Noije, Thomas A. Hughes, Ralph K. Cavin III
1994 J jnl
Circuit delay calculation considering data dependent delays.
Integr.
C. Thomas Gray, Wentai Liu, Ralph K. Cavin III, Hong-Yean Hsieh
1994 J jnl
Timing constraints for wave-pipelined systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
C. Thomas Gray, Wentai Liu, Ralph K. Cavin III
1993 J jnl
A bit-serial VLSI architecture for generating moments in real-time.
IEEE Trans. Syst. Man Cybern.
Wentai Liu, Su-shing Chen, Ralph K. Cavin III
1991 — conf
Theoretical and Practical Issues in CMOS Wave Pipelining.
VLSI
C. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III
1990 J jnl
Design of integrated circuits: directions and challenges.
Proc. IEEE
Ralph K. Cavin III, Jeffrey L. Hilbert
1990 — conf
P
ICPR (2)
C. Thomas Gray, Wentai Liu, Thomas A. Hughes, Ralph K. Cavin III, Su-shing Chen
1990 — conf
The design of a high-performance scalable architecture for image processing applications.
ASAP
C. Thomas Gray, Wentai Liu, Thomas A. Hughes, Ralph K. Cavin III
1989 J jnl
Hamiltonian Cycles in the Shuffle-Exchange Network.
IEEE Trans. Computers
Wentai Liu, Thomas H. Hildebrandt, Ralph K. Cavin III
1989 J jnl
The Semiconductor Research Corporation: Cooperative research.
Proc. IEEE
Ralph K. Cavin III, Larry W. Sumney, Robert M. Burger
1988 A* conf
Bit-level concurrency in real-time geometric feature extractions.
CVPR
Wentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III
1988 A* conf
Exploiting Bit Level Concurrency in Real-Time Geometric Feature Extractions.
ISCA
Wentai Liu, Tong-Fei Yeh, William E. Batchelor, Ralph K. Cavin III
1988 J jnl
Rasterization theory, architectures, and implementations for a class of two-dimensional problems.
Integr.
Wentai Liu, Ralph K. Cavin III
1986 J jnl
A perspective on CMOS technology trends.
Proc. IEEE
William C. Holton, Ralph K. Cavin III
1984 A* conf
Introduction to the SRC design sciences program.
DAC
Ralph K. Cavin III
1984 J jnl
The Impact of ICs on Computer Technology.
Computer
Robert M. Burger, Ralph K. Cavin III, William C. Holton, Larry W. Sumney
1983 J jnl
Microelectronic architectures and devices for signal and symbol processing.
Integr.
Ralph K. Cavin III, Noel R. Strader
1982 J jnl
Analysis of error-gradient adaptive linear estimators for a class of stationary dependent processes.
IEEE Trans. Inf. Theory
Stephen K. Jones, Ralph K. Cavin III, William M. Reed
1980 J jnl
An Efficient Computational Procedure for the Evaluation of the M/M/I Transient State Occupancy Probabilities.
IEEE Trans. Commun.
Stephen K. Jones, Ralph K. Cavin III, Donald A. Johnston
1977 J jnl
Distributed parameter system optimum control design via finite element discretization.
Autom.
Ralph K. Cavin III, S. C. Tandon
1977 J jnl
Dynamic Modeling and Control of Digital Communication Networks.
Computer
Stephen K. Jones, Ralph K. Cavin III
1977 J jnl
On the Maximum Average Throughput Rate for a Tandem Node Network.
IEEE Trans. Commun.
Stephen K. Jones, Ralph K. Cavin III, J. N. Holyoak