Ralph Gerard B. Sangalang

24 papers Journal 14Unranked 10
YearRankTypeTitle / Venue / Authors
2025 J jnl
A 4.447 mW at 100 MHz and 49.62% Uniqueness XNOR-XOR RO PUF ASIC Using 180-nm CMOS Process for IoT Security Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Chua-Chin Wang, Pradyumna Vellanki, Jian-Jie Chen, Ralph Gerard B. Sangalang
2025 J jnl
A Power-Efficient 0.5668 TOPS/W Digital Logic Accelerator Implemented Using 40-nm CMOS Process for Underwater Object Recognition Usage.
IEEE Access
Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho
2025 J jnl
An on-chip temperature sensor with 0.5 °C resolution and 0.34% linearity error using 180-nm CMOS process.
Integr.
Chua-Chin Wang, Pradyumna Vellanki, Shih-Heng Luo, Ralph Gerard B. Sangalang
2024 J jnl
A 13.73 ns Input Time Range TDA Design Based on Adjustable Current Sources Using 40-nm CMOS Process.
Circuits Syst. Signal Process.
Chua-Chin Wang, Oliver Lexter July A. Jose, Li Lin, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Anela L. Salvador
2024 — conf
A 54.61-GOPS 96.35-mW Digital Logic Accelerator For Underwater Object Recognition DNN Using 40-nm CMOS Process.
AICAS
Chua-Chin Wang, Shih-Heng Luo, Hsin-Che Wu, Ralph Gerard B. Sangalang, Chewnpu Jou, Harry Hsia, Lan-Chou Cho
2024 J jnl
A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array.
IEEE Trans. Very Large Scale Integr. Syst.
Oliver Lexter July A. Jose, Venkata Naveen Kolakaluri, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Chua-Chin Wang
2024 J jnl
A single-chip PFM-controlled LED driver with 0.5% illuminance variation.
Microelectron. J.
Chua-Chin Wang, L. S. S. Pavan Kumar Chodisetti, Pang-Yen Lou, Chen-Cheng-Hung Hung, Pradyumna Vellanki, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tirso A. Ronquillo
2024 — conf
Power Supply for Submerged Camera as Applied to Environmental Monitoring.
MCSoC
Mae Dyan E. Baynas, Anton Louise P. De Ocampo, Ralph Gerard B. Sangalang
2024 — conf
Trends in Technological Areas using Patent Analytics: A Comparative Study on the Time Series Forecasting of International Patent Classification.
ICSET
John Joshua F. Montañez, Ralph Gerard B. Sangalang
2023 — conf
A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process.
APCCAS
Ralph Gerard B. Sangalang, Wei-Zhen Chen, Chua-Chin Wang
2023 J jnl
A 1.0 fJ energy/bit single-ended 1 kb 6T SRAM implemented using 40 nm CMOS process.
IET Circuits Devices Syst.
Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng, Yi-Jen Chiu, Yu-Cheng Lin, Oliver Lexter July A. Jose
2023 J jnl
A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder.
Circuits Syst. Signal Process.
Chua-Chin Wang, Oliver Lexter July A. Jose, Wen-Shou Yang, Ralph Gerard B. Sangalang, Lean Karlo S. Tolentino, Tzung-Je Lee
2023 J jnl
A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs
Ralph Gerard B. Sangalang, Shiva Reddy, Lean Karlo S. Tolentino, You-Wei Shen, Oliver Lexter July A. Jose, Chua-Chin Wang
2023 J jnl
A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process.
Integr.
Chua-Chin Wang, Lean Karlo S. Tolentino, Shao-Wei Lu, Oliver Lexter July A. Jose, Ralph Gerard B. Sangalang, Tzung-Je Lee, Pang-Yen Lou, Wei-Chih Chang
2023 — conf
A High Resolution And Wide Range Temperature Detector Using 180-nm CMOS Process.
ICICDT
Ralph Gerard B. Sangalang, Shih-Heng Luo, Chua-Chin Wang
2023 — conf
Developing an LTE Learning Material: Experiences from a University in a Developing Country.
ICIT
Leinard C. Lontoc, Marjorie H. Basco, Vannesa Ann P. Sulit, Genesis Aubrey M. Magpantay, Mirasol C. Dilay, Ralph Gerard B. Sangalang
2023 — conf
FPGA-Based Radio Transceiver Using the TV White Space for Disaster Response Operation.
ICIT
Khryzz Lyden G. Cueto, Ricky Mae V. Santos, Claudette Jane C. Hilario, John Carl V. Aggari, Ralph Gerard B. Sangalang
2023 — conf
Passiveless Digitally Controlled Oscillator With Embedded PVT Detector Using 40-nm CMOS.
ASICON
Ralph Gerard B. Sangalang, You-Wei Shen, Shiva Reddy, Lean Karlo S. Tolentino, Chua-Chin Wang
2022 J jnl
A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chua-Chin Wang, Ralph Gerard B. Sangalang, Chien-Ping Kuo, Hsin-Che Wu, Yi Hsu, Shen-Fu Hsiao, Chia-Hung Yeh
2022 — conf
A Power Effective DLA for PBs in Opto-Electrical Neural Network Architecture.
APCCAS
Ralph Gerard B. Sangalang, Shih-Heng Luo, Hsin-Che Wu, Bao-Qi He, Shen-Fu Hsiao, Chua-Chin Wang, Chewnpu Jou, Harry Hsia, Douglas C.-H. Yu
2022 J jnl
Design of a control architecture for an underwater remotely operated vehicle (ROV) used for search and rescue operations.
Kybernetika
Ralph Gerard B. Sangalang, Diether Jhay S. Masangcay, Cleo Martin R. Torino, Diane Jelyn C. Gutierrez
2022 — conf
Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process.
ICICDT
Shiva Reddy, Ralph Gerard B. Sangalang, Chua-Chin Wang
2021 J jnl
A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit.
IEEE Trans. Circuits Syst. II Express Briefs
Chua-Chin Wang, Ralph Gerard B. Sangalang, I-Ting Tseng
2021 J jnl
An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μm HV CMOS.
Microelectron. J.
Chua-Chin Wang, Oliver Lexter July A. Jose, Po-Kai Su, Lean Karlo S. Tolentino, Ralph Gerard B. Sangalang, Jessica Velasco, Tzung-Je Lee