Rakshith Saligram

12 papers A 3C 1Journal 2Unranked 6

Year	Rank	Type	Title / Venue / Authors
2024	A	`conf`	Cooling the Chaos: Mitigating the Effect of Threshold Voltage Variation in Cryogenic CMOS Memories. ISLPED Rakshith Saligram, Amol D. Gaidhane, Yu Kevin Cao, Suman Datta, Arijit Raychowdhury
2024	A	`conf`	Cryogenic Operation of Computing-In-Memory based Spiking Neural Network. ISLPED Laith A. Shamieh, Wei-Chun Wang, Shida Zhang, Rakshith Saligram, Amol D. Gaidhane, Yu Cao, Arijit Raychowdhury, Suman Datta, Saibal Mukhopadhyay
2023	A	`conf`	Cryogenic CMOS as an Enabler for Low Power Dynamic Logic. ISLPED Rakshith Saligram, Suman Datta, Arijit Raychowdhury
2022	J	`jnl`	Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses. IEEE Trans. Circuits Syst. I Regul. Pap. Rakshith Saligram, Suman Datta, Arijit Raychowdhury
2022	—	`conf`	Multi-bit per-cell 1T SiGe Floating Body RAM for Cache Memory in Cryogenic Computing. VLSI Technology and Circuits Wriddhi Chakraborty, P. Shrestha, A. Gupta, Rakshith Saligram, Samuel Spetalnick, J. Campbell, Arijit Raychowdhury, Suman Datta
2021	—	`conf`	A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance. CICC Rakshith Saligram, Divya Prasad, David Pietromonaco, Arijit Raychowdhury, Brian Cline
2021	—	`conf`	CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications. CICC Rakshith Saligram, Suman Datta, Arijit Raychowdhury
2020	C	`conf`	A Model Study of Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication in 2.5D Integration. VLSI-SOC Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury
2020	—	`conf`	Multilevel Signaling for High-Speed Chiplet-to-Chiplet Communication. VLSI-SoC (Selected Papers) Rakshith Saligram, Ankit Kaul, Muhannad S. Bakir, Arijit Raychowdhury
2013	—	`conf`	Design of Low Logical Cost Conservative Reversible Adders Using Novel PCTG. ISED Rakshith Saligram
2013	J	`jnl`	Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit. CoRR Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A. Kulkarni, H. R. Bhagyalakshmi, M. K. Venkatesha
2013	—	`conf`	Towards the design of fault tolerant reversible circuits components of ALU using new PCMF gate. ICACCI Rakshith Saligram, T. R. Rakshith