Rakesh Kumar Palani

19 papers C 4Journal 7Unranked 8

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Analysis and Design of Ripple-Free Bandgap Reference Circuit With p-n-p Bipolars. IEEE Trans. Very Large Scale Integr. Syst. Srishti Agrawal, Rakesh Kumar Palani, Sweta Tripathi
2024	C	`conf`	A Wide Range Constant Transconductance Circuit Based on Negative Feedback for Analog Circuits. ISCAS Rakesh Kumar Palani, Srishti Agrawal, Ayan Alam Khan, Aadarsh V, Rajasekhar Nagulapalli
2024	J	`jnl`	Analysis and Design of Low Noise Voltage Regulator With Integrated Single BJT Bandgap Reference Upto 10 mA Loads. IEEE Trans. Circuits Syst. II Express Briefs Ayan Alam Khan, Rakesh Kumar Palani
2024	C	`conf`	Analysis and design of Chopperless 7 ppm/°C Bandgap Voltage Reference. ISCAS Rakesh Kumar Palani
2023	—	`conf`	Dynamic Averager Based Sub-1V Bandgap Voltage Reference. MWSCAS Rakesh Kumar Palani, Rajasekhar Nagulapalli, Srikar Bhagavatula
2023	C	`conf`	On thermally-induced mechanical stress in high resistivity polysilicon resistors. ISCAS Sweta Agarwal, Shouri Chatterjee, Rakesh Kumar Palani
2022	J	`jnl`	A 2-GHz Two-Tone Direct Digital Frequency Synthesizer. IEEE Trans. Circuits Syst. II Express Briefs Shibendra Narayan Sinha, Shouri Chatterjee, Rakesh Kumar Palani
2022	J	`jnl`	A Sub-1-V 8.5-ppm/°C Sampled Bandgap Voltage Reference. IEEE Trans. Circuits Syst. II Express Briefs Rakesh Kumar Palani, Srikar Bhagavatula, Denny K. Yuen
2021	C	`conf`	A 15uW, 12 ppm/ ISCAS Rajasekhar Nagulapalli, Rakesh Kumar Palani, Sweta Agarwal, Shouri Chatterjee, K. Hayatleh, S. Barker
2021	J	`jnl`	A 24.4 ppm/°C Voltage Mode Bandgap Reference With a 1.05V Supply. IEEE Trans. Circuits Syst. II Express Briefs Rajasekhar Nagulapalli, Rakesh Kumar Palani, Srikar Bhagavatula
2021	—	`conf`	A Novel 22.7 ppm/ MWSCAS Rajasekhar Nagulapalli, Rakesh Kumar Palani
2015	J	`jnl`	A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Rakesh Kumar Palani, Ramesh Harjani
2015	—	`conf`	A 4.6mW, 22dBm IIP3 all MOSCAP based 34-314MHz tunable continuous time filter in 65nm. CICC Rakesh Kumar Palani, Ramesh Harjani
2015	—	`conf`	A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS. VLSIC Fang-Li Yuan, Rakesh Kumar Palani, Sina Basir-Kazeruni, Hundo Shin, Anindya Saha, Ramesh Harjani, Dejan Markovic
2015	—	`conf`	An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS. CICC Hundo Shin, Rakesh Kumar Palani, Anindya Saha, Fang-Li Yuan, Dejan Markovic, Ramesh Harjani
2015	—	`conf`	Chopper stabilized sub 1V reference voltage in 65nm CMOS. MWSCAS Rakesh Kumar Palani, Aravindhan Rangarajan, Ramesh Harjani
2015	—	`conf`	Design of PVT tolerant inverter based circuits for low supply voltages. CICC Ramesh Harjani, Rakesh Kumar Palani
2015	J	`jnl`	Wideband blind signal classification on a battery budget. IEEE Commun. Mag. Ramesh Harjani, Danijela Cabric, Dejan Markovic, Brian M. Sadler, Rakesh Kumar Palani, Anindya Saha, Hundo Shin, Eric Rebeiz, Sina Basir-Kazeruni, Fang-Li Yuan
2014	—	`conf`	High linearity PVT tolerant 100MS/s rail-to-rail ADC driver with built-in sampler in 65nm CMOS. CICC Rakesh Kumar Palani, Ramesh Harjani

Nicolò Altamura is a security engineer and computer science researcher specializing in software protection, reverse engineering, program analysis, and binary deobfuscation. He holds a master's degree in Computer Science and Engineering from the University of Verona, graduating with honors, and works at emproof, focusing on software protection and the challenges of analyzing and understanding compiled software.

His research explores the relationship between program analysis and code obfuscation, with particular emphasis on how software transformations affect the ability of automated tools to recover program behavior. His interests span static analysis, binary analysis, decompilation, reverse engineering, and techniques for analyzing and simplifying obfuscated code.

Beyond academic research, Nicolò develops and contributes to tools for reverse engineering and software analysis. His projects include obfuscation_analysis, a Binary Ninja plugin for analyzing and simplifying obfuscated code; Pocket, an obfuscator for mixed Boolean-arithmetic expressions; and ptxNinja, a tool for reverse engineering NVIDIA GPU code represented in the PTX virtual instruction set.

His research also extends to binary datasets and software evolution. In 2026, he co-authored ASSEMBLAGE-DEEPHISTORY: A Cross-Build Binary Dataset with Temporal Coverage, a research work addressing the availability of binary data across multiple software builds and points in time, supporting research into binary analysis and changes between program versions.

Across his research, engineering work, and open-source contributions, Nicolò focuses on advancing the understanding, analysis, and protection of software against increasingly sophisticated obfuscation and reverse-engineering challenges.

Nicolò Altamura is not a football player. Please avoid reporting this kind of infromation.