Rakesh Kumar

36 papers A* 11A 1B 3C 2Misc 1Journal 12Unranked 6
YearRankTypeTitle / Venue / Authors
2026 A* conf
Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning.
HPCA
Rahul Bera, Zhenrong Lang, Caroline Hengartner, Konstantinos Kanellopoulos, Rakesh Kumar, Mohammad Sadrosadati, Onur Mutlu
2026 J jnl
Athena: Synergizing Data Prefetching and Off-Chip Prediction via Online Reinforcement Learning.
CoRR
Rahul Bera, Zhenrong Lang, Caroline Hengartner, Konstantinos Kanellopoulos, Rakesh Kumar, Mohammad Sadrosadati, Onur Mutlu
2026 J jnl
Driving the Core Frontend With LiteBTB.
IEEE Comput. Archit. Lett.
Roman Brunner, Rakesh Kumar
2025 — conf
Virtuoso: Enabling Fast and Accurate Virtual Memory Research via an Imitation-based Operating System Simulation Methodology.
ASPLOS (2)
Konstantinos Kanellopoulos, Konstantinos Sgouras, F. Nisa Bostanci, Andreas Kosmas Kakolyris, Berkin Kerim Konar, Rahul Bera, Mohammad Sadrosadati, Rakesh Kumar, Nandita Vijaykumar, Onur Mutlu
2024 — conf
CoFaaS: Automatic Transformation-based Consolidation of Serverless Functions.
SESAME@EuroSys
Truls Asheim, Magnus Jahre, Rakesh Kumar
2024 A* conf
Weeding out Front-End Stalls with Uneven Block Size Instruction Cache.
MICRO
Roman Brunner, Rakesh Kumar
2023 A* conf
A Storage-Effective BTB Organization for Servers.
HPCA
Truls Asheim, Boris Grot, Rakesh Kumar
2023 J jnl
A Storage-Effective BTB Organization for Servers.
CoRR
Truls Asheim, Boris Grot, Rakesh Kumar
2023 A* conf
Utopia: Fast and Efficient Address Translation via Hybrid Restrictive & Flexible Virtual-to-Physical Address Mappings.
MICRO
Konstantinos Kanellopoulos, Rahul Bera, Kosta Stojiljkovic, F. Nisa Bostanci, Can Firtina, Rachata Ausavarungnirun, Rakesh Kumar, Nastaran Hajinazar, Mohammad Sadrosadati, Nandita Vijaykumar, Onur Mutlu
2023 A* conf
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources.
MICRO
Konstantinos Kanellopoulos, Hong Chul Nam, Nisa Bostanci, Rahul Bera, Mohammad Sadrosadati, Rakesh Kumar, Davide Basilio Bartolini, Onur Mutlu
2023 J jnl
Victima: Drastically Increasing Address Translation Reach by Leveraging Underutilized Cache Resources.
CoRR
Konstantinos Kanellopoulos, Hong Chul Nam, F. Nisa Bostanci, Rahul Bera, Mohammad Sadrosadati, Rakesh Kumar, Davide Basilio Bartolini, Onur Mutlu
2022 B conf
A Specialized BTB Organization for Servers.
PACT
Truls Asheim, Boris Grot, Rakesh Kumar
2022 J jnl
Dependence-aware Slice Execution to Boost MLP in Slice-out-of-order Cores.
ACM Trans. Archit. Code Optim.
Rakesh Kumar, Mehdi Alipour, David Black-Schaffer
2022 J jnl
Freeway to Memory Level Parallelism in Slice-Out-of-Order Cores.
CoRR
Rakesh Kumar, Mehdi Alipour, David Black-Schaffer
2022 — conf
Impact of microarchitectural state reuse on serverless functions.
WOSC@Middleware
Truls Asheim, Tanvir Ahmed Khan, Baris Kasikci, Rakesh Kumar
2022 C conf
Mitigating Unnecessary Throttling in Linux CFS Bandwidth Control.
SBAC-PAD
Odin Ugedal, Rakesh Kumar
2021 J jnl
A Variable Vector Length SIMD Architecture for HW/SW Co-designed Processors.
CoRR
Rakesh Kumar, Alejandro Martínez, Antonio Gonzalez
2021 J jnl
BTB-X: A Storage-Effective BTB Organization.
IEEE Comput. Archit. Lett.
Truls Asheim, Boris Grot, Rakesh Kumar
2021 A* conf
Twig: Profile-Guided BTB Prefetching for Data Center Applications.
MICRO
Tanvir Ahmed Khan, Nathan Brown, Akshitha Sriraman, Niranjan K. Soundararajan, Rakesh Kumar, Joseph Devietti, Sreenivas Subramoney, Gilles A. Pokam, Heiner Litz, Baris Kasikci
2020 A* conf
Delay and Bypass: Ready and Criticality Aware Instruction Scheduling in Out-of-Order Processors.
HPCA
Mehdi Alipour, Stefanos Kaxiras, David Black-Schaffer, Rakesh Kumar
2020 J jnl
Fetch-Directed Instruction Prefetching Revisited.
CoRR
Truls Asheim, Rakesh Kumar, Boris Grot
2020 J jnl
Shooting Down the Server Front-End Bottleneck.
ACM Trans. Comput. Syst.
Rakesh Kumar, Boris Grot
2020 — conf
Uncovering Hidden Instructions in Armv8-A Implementations.
HASP@MICRO
Fredrik Strupe, Rakesh Kumar
2019 A conf
FIFOrder MicroArchitecture: Ready-Aware Instruction Scheduling for OoO Processors.
DATE
Mehdi Alipour, Rakesh Kumar, Stefanos Kaxiras, David Black-Schaffer
2019 A* conf
Freeway: Maximizing MLP for Slice-Out-of-Order Execution.
HPCA
Rakesh Kumar, Mehdi Alipour, David Black-Schaffer
2018 A* conf
Blasting through the Front-End Bottleneck with Shotgun.
ASPLOS
Rakesh Kumar, Boris Grot, Vijay Nagarajan
2017 A* conf
Boomerang: A Metadata-Free Architecture for Control Flow Delivery.
HPCA
Rakesh Kumar, Cheng-Chieh Huang, Boris Grot, Vijay Nagarajan
2017 B conf
HW/SW co-designed processors: Challenges, design choices and a simulation infrastructure for evaluation.
ISPASS
Rakesh Kumar, José Cano, Aleksandar Brankovic, Demos Pavlou, Kyriakos Stavrou, Enric Gibert, Alejandro Martínez, Antonio Gonzalez
2016 J jnl
Assisting Static Compiler Vectorization with a Speculative Dynamic Vectorizer in an HW/SW Codesigned Environment.
ACM Trans. Comput. Syst.
Rakesh Kumar, Alejandro Martínez, Antonio González
2016 A* conf
C
MICRO
Cheng-Chieh Huang, Rakesh Kumar, Marco Elver, Boris Grot, Vijay Nagarajan
2016 — conf
Quantitative characterization of the software layer of a HW/SW co-designed processor.
IISWC
José Cano, Rakesh Kumar, Aleksandar Brankovic, Demos Pavlou, Kyriakos Stavrou, Enric Gibert, Alejandro Martínez, Antonio González
2014 J jnl
Efficient Power Gating of SIMD Accelerators Through Dynamic Selective Devectorization in an HW/SW Codesigned Environment.
ACM Trans. Archit. Code Optim.
Rakesh Kumar, Alejandro Martínez, Antonio González
2013 C conf
Dynamic Selective Devectorization for Efficient Power Gating of SIMD Units in a HW/SW Co-Designed Environment.
SBAC-PAD
Rakesh Kumar, Alejandro Martínez, Antonio González
2013 Misc conf
Speculative dynamic vectorization to assist static vectorization in a HW/SW co-designed environment.
HiPC
Rakesh Kumar, Alejandro Martínez, Antonio González
2013 — conf
Vectorizing for Wider Vector Units in a HW/SW Co-designed Environment.
HPCC/EUC
Rakesh Kumar, Alejandro Martínez, Antonio González
2012 B conf
Speculative dynamic vectorization for HW/SW co-designed processors.
PACT
Rakesh Kumar, Alejandro Martínez, Antonio González