Rakesh Kumar - RankMe

117 papers A* 39A 18B 4C 4Misc 7Journal 31Unranked 12

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Waferscale Network Switches. IEEE Micro Shuangliang David Chen, Saptadeep Pal, Rakesh Kumar
2025	A	`conf`	Waferscale Silicon Photonics Systems: A Cost-Benefit Analysis and Optimization. ICCAD Robert Bao, Zongrui Cai, Shuangliang Chen, Ajay Joshi, Darius Bunandar, Rakesh Kumar
2024	J	`jnl`	Programmable Olfactory Computing. IEEE Micro Nathaniel Bleier, Abigail Wezelis, Lav R. Varshney, Rakesh Kumar
2024	A*	`conf`	Waferscale Network Switches. ISCA Shuangliang Chen, Saptadeep Pal, Rakesh Kumar
2023	A	`conf`	Exploiting Short Application Lifetimes for Low Cost Hardware Encryption in Flexible Electronics. DATE Nathaniel Bleier, Muhammad Husnain Mubarik, Suman Balaji, Francisco Rodriguez, Antony Sou, Scott White, Rakesh Kumar
2023	A*	`conf`	Hardware Acceleration of Neural Graphics. ISCA Muhammad Husnain Mubarik, Ramakrishna Kanungo, Tobias Zirr, Rakesh Kumar
2023	J	`jnl`	Hardware Acceleration of Neural Graphics. CoRR Muhammad Husnain Mubarik, Ramakrishna Kanungo, Tobias Zirr, Rakesh Kumar
2023	A*	`conf`	Programmable Olfactory Computing. ISCA Nathaniel Bleier, Abigail Wezelis, Lav R. Varshney, Rakesh Kumar
2023	A*	`conf`	Space Microdatacenters. MICRO Nathaniel Bleier, Muhammad Husnain Mubarik, Gary R. Swenson, Rakesh Kumar
2023	J	`jnl`	Understanding Interactions Between Chip Architecture and Uncertainties in Semiconductor Supply and Demand. CoRR Ramakrishna Kanungo, Swamynathan Siva, Nathaniel Bleier, Muhammad Husnain Mubarik, Lav R. Varshney, Rakesh Kumar
2022	A*	`conf`	FlexiCores: low footprint, high yield, field reprogrammable flexible microprocessors. ISCA Nathaniel Bleier, Calvin Lee, Francisco Rodriguez, Antony Sou, Scott White, Rakesh Kumar
2022	A*	`conf`	Rethinking programmable wearable processors. ISCA Nathaniel Bleier, Muhammad Husnain Mubarik, Srijan Chakraborty, Shreyas Kishore, Rakesh Kumar
2021	J	`jnl`	Byte-Select Compression. ACM Trans. Archit. Code Optim. Matthew Tomei, Shomit Das, Mohammad Seyedzadeh, Philip Bedoukian, Bradford M. Beckmann, Rakesh Kumar, David A. Wood
2021	A*	`conf`	Designing a 2048-Chiplet, 14336-Core Waferscale Processor. DAC Saptadeep Pal, Jingyang Liu, Irina Alam, Nicholas Cebry, Haris Suhail, Shi Bu, Subramanian S. Iyer, Sudhakar Pamarti, Rakesh Kumar, Puneet Gupta
2021	A	`conf`	Printed Stochastic Computing Neural Networks. DATE Dennis D. Weller, Nathaniel Bleier, Michael Hefenbrock, Jasmin Aghassi-Hagmann, Michael Beigl, Rakesh Kumar, Mehdi B. Tahoori
2021	A*	`conf`	Property-driven Automatic Generation of Reduced-ISA Hardware. DAC Nathaniel Bleier, John Sartori, Rakesh Kumar
2021	J	`jnl`	When Tiny Goes Big: A Computer Architect's View of the Emerging Internet of Tiny Things. GetMobile Mob. Comput. Commun. Rakesh Kumar
2020	J	`jnl`	Design Space Exploration for Chiplet-Assembly-Based Processors. IEEE Trans. Very Large Scale Integr. Syst. Saptadeep Pal, Daniel Petrisko, Rakesh Kumar, Puneet Gupta
2020	A*	`conf`	Hardware Acceleration of Graph Neural Networks. DAC Adam Auten, Matthew Tomei, Rakesh Kumar
2020	A*	`conf`	Printed Machine Learning Classifiers. MICRO Muhammad Husnain Mubarik, Dennis D. Weller, Nathaniel Bleier, Matthew Tomei, Jasmin Aghassi-Hagmann, Mehdi B. Tahoori, Rakesh Kumar
2020	A*	`conf`	Printed Microprocessors. ISCA Nathaniel Bleier, Muhammad Husnain Mubarik, Farhan Rasheed, Jasmin Aghassi-Hagmann, Mehdi B. Tahoori, Rakesh Kumar
2019	A*	`conf`	Architecting Waferscale Processors - A GPU Case Study. HPCA Saptadeep Pal, Daniel Petrisko, Matthew Tomei, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar
2019	Misc	`conf`	SDN Resiliency to Controller Failure in Mobile Contexts. WSC David M. Nicol, Rakesh Kumar
2019	—	`conf`	Sensor Training Data Reduction for Autonomous Vehicles. HotEdgeVideo@MobiCom Matthew Tomei, Alexander G. Schwing, Satish Narayanasamy, Rakesh Kumar
2018	A*	`conf`	A Case for Packageless Processors. HPCA Saptadeep Pal, Daniel Petrisko, Adeel Ahmad Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar
2018	J	`jnl`	Bespoke Processors for Applications with Ultra-Low Area and Power Constraints. IEEE Micro Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori
2018	A*	`conf`	Guaranteeing Local Differential Privacy on Ultra-Low-Power Systems. ISCA Woo-Seok Choi, Matthew Tomei, Jose Rodrigo Sanchez Vicarte, Pavan Kumar Hanumolu, Rakesh Kumar
2018	B	`conf`	Network Coding for Critical Infrastructure Networks. ICNP Rakesh Kumar, Vignesh Babu, David M. Nicol
2018	J	`jnl`	Network Coding for Critical Infrastructure Networks. CoRR Rakesh Kumar, Vignesh Babu, David M. Nicol
2018	J	`jnl`	Temporal Integration of Emulation and Network Simulators on Linux Multiprocessors. ACM Trans. Model. Comput. Simul. Jereme Lamps, Vignesh Babu, David M. Nicol, Vladimir Adam, Rakesh Kumar
2017	A*	`conf`	Bespoke Processors for Applications with Ultra-low Area and Power Constraints. ISCA Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori
2017	J	`jnl`	Determining Application-Specific Peak Power and Energy Requirements for Ultra-Low-Power Processors. ACM Trans. Comput. Syst. Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori
2017	A*	`conf`	Determining Application-specific Peak Power and Energy Requirements for Ultra-low Power Processors. ASPLOS Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori
2017	A*	`conf`	Enabling Effective Module-Oblivious Power Gating for Embedded Processors. HPCA Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori
2017	Misc	`conf`	Melody: Synthesized datasets for evaluating intrusion detection systems for the smart grid. WSC Vignesh Babu, Rakesh Kumar, Hoang Hai Nguyen, David M. Nicol, Kartik Palani, Elizabeth Reed
2017	A*	`conf`	Software-based gate-level information flow security for IoT systems. MICRO Hari Cherupalli, Henry Duwe, Weidong Ye, Rakesh Kumar, John Sartori
2017	A*	`conf`	Understanding and Optimizing Power Consumption in Memory Networks. HPCA Xun Jian, Pavan Kumar Hanumolu, Rakesh Kumar
2016	—	`conf`	A Unified Framework for Error Correction in On-chip Memories. DSN Workshops Frederic Sala, Henry Duwe, Lara Dolecek, Rakesh Kumar
2016	A*	`conf`	Approximate bitcoin mining. DAC Matthew Vilim, Henry Duwe, Rakesh Kumar
2016	A	`conf`	Bit Serializing a Microprocessor for Ultra-low-power. ISLPED Matthew Tomei, Henry Duwe, Nam Sung Kim, Rakesh Kumar
2016	—	`conf`	Efficient Monte Carlo Evaluation of SDN Resiliency. SIGSIM-PADS David M. Nicol, Rakesh Kumar
2016	A*	`conf`	Exploiting Dynamic Timing Slack for Energy Efficiency in Ultra-Low-Power Embedded Systems. ISCA Hari Cherupalli, Rakesh Kumar, John Sartori
2016	A*	`conf`	Parity Helix: Efficient protection for single-dimensional faults in multi-dimensional memory systems. HPCA Xun Jian, Vilas Sridharan, Rakesh Kumar
2016	A*	`conf`	Rescuing Uncorrectable Fault Patterns in On-Chip Memories through Error Pattern Transformation. ISCA Henry Duwe, Xun Jian, Daniel Petrisko, Rakesh Kumar
2016	—	`conf`	Validating resiliency in Software Defined Networks for smart grids. SmartGridComm Rakesh Kumar, David M. Nicol
2015	A*	`conf`	Correction prediction: Reducing error correction latency for on-chip memories. HPCA Henry Duwe, Xun Jian, Rakesh Kumar
2015	J	`jnl`	NSF expedition on variability-aware software: Recent results and contributions. it Inf. Technol. Lucas Francisco Wanner, Liangzhen Lai, Abbas Rahimi, Mark Gottscho, Pietro Mercati, Chu-Hsiang Huang, Frederic Sala, Yuvraj Agarwal, Lara Dolecek, Nikil D. Dutt, Puneet Gupta, Rajesh K. Gupta, Ranjit Jhala, Rakesh Kumar, Sorin Lerner, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava, Steven Swanson, Dennis Sylvester, Yuanyuan Zhou
2014	J	`jnl`	Better-Than-Worst-Case Design: Progress and Opportunities. J. Comput. Sci. Technol. Jason Cong, Henry Duwe, Rakesh Kumar, Sen Li
2014	A	`conf`	ECC Parity: A Technique for Efficient Memory Error Resilience for Multi-Channel Memory Systems. SC Xun Jian, Rakesh Kumar
2014	A	`conf`	Software canaries: software-based path delay fault testing for variation-aware energy-efficient design. ISLPED John Sartori, Rakesh Kumar
2013	A*	`conf`	Adaptive Reliability Chipkill Correct (ARCC). HPCA Xun Jian, Rakesh Kumar
2013	A	`conf`	An algorithmic approach to error localization and partial recomputation for low-overhead fault tolerance. DSN Joseph Sloan, Rakesh Kumar, Greg Bronevetsky
2013	C	`conf`	Analyzing Reliability of Memory Sub-systems with Double-Chipkill Detect/Correct. PRDC Xun Jian, Nathan DeBardeleben, Sean Blanchard, Vilas Sridharan, Rakesh Kumar
2013	J	`jnl`	Branch and Data Herding: Reducing Control and Memory Divergence for Error-Tolerant GPU Applications. IEEE Trans. Multim. John Sartori, Rakesh Kumar
2013	J	`jnl`	Enhancing the Efficiency of Energy-Constrained DVFS Designs. IEEE Trans. Very Large Scale Integr. Syst. Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2013	J	`jnl`	Exploiting Timing Error Resilience in Processor Architecture. ACM Trans. Embed. Comput. Syst. John Sartori, Rakesh Kumar
2013	J	`jnl`	High Performance, Energy Efficient Chipkill Correct Memory with Multidimensional Parity. IEEE Comput. Archit. Lett. Xun Jian, John Sartori, Henry Duwe, Rakesh Kumar
2013	A	`conf`	Low-power, low-storage-overhead chipkill correct via multi-line error correction. SC Xun Jian, Henry Duwe, John Sartori, Vilas Sridharan, Rakesh Kumar
2013	Misc	`conf`	Markov chain algorithms: A template for building future robust low power systems. ACSSC Biplab Deka, Alex A. Birklykke, Henry Duwe, Vikash K. Mansinghka, Rakesh Kumar
2013	A	`conf`	On reconfiguration-oriented approximate adder design and its application. ICCAD Rong Ye, Ting Wang, Feng Yuan, Rakesh Kumar, Qiang Xu
2013	C	`conf`	Statistical analysis and modeling for error composition in approximate computation circuits. ICCD Wei-Ting Jonas Chan, Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2013	J	`jnl`	Underdesigned and Opportunistic Computing in Presence of Hardware Variability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Puneet Gupta, Yuvraj Agarwal, Lara Dolecek, Nikil D. Dutt, Rajesh K. Gupta, Rakesh Kumar, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava, Steven Swanson, Dennis Sylvester
2012	A	`conf`	Algorithmic approaches to low overhead fault detection for sparse linear algebra. DSN Joseph Sloan, Rakesh Kumar, Greg Bronevetsky
2012	B	`conf`	Branch and data herding: reducing control and memory divergence for error-tolerant GPU applications. PACT John Sartori, Rakesh Kumar
2012	A*	`conf`	Compiling for energy efficiency on timing speculative processors. DAC John Sartori, Rakesh Kumar
2012	A	`conf`	On logic synthesis for timing speculation. ICCAD Yuxi Liu, Rong Ye, Feng Yuan, Rakesh Kumar, Qiang Xu
2012	A*	`conf`	On software design for stochastic processors. DAC Joseph Sloan, John Sartori, Rakesh Kumar
2012	A*	`conf`	Power balanced pipelines. HPCA John Sartori, Ben Ahrens, Rakesh Kumar
2012	J	`jnl`	Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2011	—	`conf`	A hardware acceleration technique for gradient descent and conjugate gradient. SASP David Kesler, Biplab Deka, Rakesh Kumar
2011	Misc	`conf`	Architecting processors to allow voltage/reliability tradeoffs. CASES John Sartori, Rakesh Kumar
2011	J	`jnl`	MOPED: Accelerating Data Communication on Future CMPs. IEEE Micro Junli Gu, Yihe Sun, Steven S. Lumetta, Rakesh Kumar
2011	A*	`conf`	MOPED: Orchestrating interprocess message data on CMPs. HPCA Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Sun
2011	A	`conf`	On the efficacy of NBTI mitigation techniques. DATE Tuck-Boon Chan, John Sartori, Puneet Gupta, Rakesh Kumar
2011	J	`jnl`	Stochastic Computing. Found. Trends Electron. Des. Autom. John Sartori, Rakesh Kumar
2011	Misc	`conf`	Stochastic computing: embracing errors in architectureand design of processors and applications. CASES John Sartori, Joseph Sloan, Rakesh Kumar
2011	—	`ch.`	The Case for Message Passing on Many-Core Chips. Multiprocessor System-on-Chip Rakesh Kumar, Timothy G. Mattson, Gilles Pokam, Rob F. Van der Wijngaart
2010	J	`jnl`	A Workload-Adaptive and Reconfigurable Bus Architecture for Multicore Processors. Int. J. Reconfigurable Comput. Shoaib Akram, Alexandros Papakonstantinou, Rakesh Kumar, Deming Chen
2010	A	`conf`	A numerical optimization-based methodology for application robustification: Transforming applications for error tolerance. DSN Joseph Sloan, David Kesler, Rakesh Kumar, Ali Rahimi
2010	—	`conf`	Accelerating data movement on future chip multi-processors. IFMT Junli Gu, Rakesh Kumar, Steven S. Lumetta, Yihe Sun
2010	A*	`conf`	Designing a processor from the ground up to allow voltage/reliability tradeoffs. HPCA Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2010	—	`conf`	Low-Overhead, High-Speed Multi-core Barrier Synchronization. HiPEAC John Sartori, Rakesh Kumar
2010	C	`conf`	Optimal power/performance pipelining for error resilient processors. ICCD Nicolas Zea, John Sartori, Ben Ahrens, Rakesh Kumar
2010	—	`conf`	Overscaling-friendly timing speculation architectures. ACM Great Lakes Symposium on VLSI John Sartori, Rakesh Kumar
2010	A*	`conf`	Recovery-driven design: a power minimization methodology for error-tolerant processor modules. DAC Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2010	A	`conf`	Scalable stochastic processors. DATE Sriram Narayanan, John Sartori, Rakesh Kumar, Douglas L. Jones
2010	—	`conf`	Slack redistribution for graceful degradation under voltage overscaling. ASP-DAC Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori
2010	A*	`conf`	Stochastic computation. DAC Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, Douglas L. Jones
2010	—	`conf`	Variation-aware speed binning of multi-core processors. ISQED John Sartori, Aashish Pant, Rakesh Kumar, Puneet Gupta
2009	A	`conf`	Distributed peak power management for many-core architectures. DATE John Sartori, Rakesh Kumar
2009	J	`jnl`	Introduction to the special issue on the 2008 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'08). SIGARCH Comput. Archit. News Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen
2009	C	`conf`	Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. IOLTS Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Christos A. Papachristou
2009	A*	`conf`	Reducing peak power with a table-driven adaptive processor core. MICRO Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar
2009	Misc	`conf`	Three scalable approaches to improving many-core throughput for a given peak power budget. HiPC John Sartori, Rakesh Kumar
2009	Misc	`conf`	Towards scalable reliability frameworks for error prone CMPs. CASES Joseph Sloan, Rakesh Kumar
2009	—	`conf`	Workload adaptive shared memory multicore processors with reconfigurable interconnects. SASP Shoaib Akram, Rakesh Kumar, Deming Chen
2008	J	`jnl`	Introduction to the special issue on the 2007 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'07). SIGARCH Comput. Archit. News Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen
2008	J	`jnl`	Servo: a programming model for many-core computing. SIGARCH Comput. Archit. News Nicolas Zea, John Sartori, Rakesh Kumar
2007	J	`jnl`	Introduction to the special issue on the 2006 workshop on design, analysis, and simulation of chip multiprocessors: (dasCMP'06). SIGARCH Comput. Archit. News Dean M. Tullsen, Rakesh Kumar, Norman P. Jouppi
2007	B	`conf`	Proximity-aware directory-based coherence for multi-core processor architectures. SPAA Jeffery A. Brown, Rakesh Kumar, Dean M. Tullsen
2007	J	`jnl`	The architecture of Efficient Multi-Core Processors: A Holistic Approach. Adv. Comput. Rakesh Kumar, Dean M. Tullsen
2006	A	`conf`	Application-specific customization of parameterized FPGA soft-core processors. ICCAD David Sheldon, Rakesh Kumar, Roman L. Lysecky, Frank Vahid, Dean M. Tullsen
2006	A	`conf`	Conjoining soft-core FPGA processors. ICCAD David Sheldon, Rakesh Kumar, Frank Vahid, Dean M. Tullsen, Roman L. Lysecky
2006	B	`conf`	Core architecture optimization for heterogeneous chip multiprocessors. PACT Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi
2006	A	`conf`	Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors. IPDPS Matthew De Vuyst, Rakesh Kumar, Dean M. Tullsen
2006	—	`—`	Holistic design for multi-core architectures. Rakesh Kumar
2005	J	`jnl`	Heterogeneous Chip Multiprocessors. Computer Rakesh Kumar, Dean M. Tullsen, Norman P. Jouppi, Parthasarathy Ranganathan
2005	A*	`conf`	Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling. ISCA Rakesh Kumar, Victor V. Zyuban, Dean M. Tullsen
2005	J	`jnl`	Introduction to the special issue on the 2005 workshop on design, analysis, and simulation of chip multiprocessors (dasCMP'05). SIGARCH Comput. Archit. News Norman P. Jouppi, Rakesh Kumar, Dean M. Tullsen
2005	J	`jnl`	The Danger of Interval-Based Power Efficiency Metrics: When Worst Is Best. IEEE Comput. Archit. Lett. Yiannakis Sazeides, Rakesh Kumar, Dean M. Tullsen, Theofanis Constantinou
2004	A*	`conf`	Balanced Multithreading: Increasing Throughput via a Low Cost Multithreading Hierarchy. MICRO Eric Tune, Rakesh Kumar, Dean M. Tullsen, Brad Calder
2004	A*	`conf`	Conjoined-Core Chip Multiprocessing. MICRO Rakesh Kumar, Norman P. Jouppi, Dean M. Tullsen
2004	A*	`conf`	Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. ISCA Rakesh Kumar, Dean M. Tullsen, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas
2003	J	`jnl`	Processor Power Reduction Via Single-ISA Heterogeneous Multi-Core Architectures. IEEE Comput. Archit. Lett. Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen
2003	A*	`conf`	Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction. MICRO Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, Parthasarathy Ranganathan, Dean M. Tullsen
2002	A*	`conf`	Compiling for instruction cache performance on a multithreaded architecture. MICRO Rakesh Kumar, Dean M. Tullsen
2002	—	`conf`	Software Energy Optimization of Real Time Preemptive Tasks by Minimizing Cache-Related Preemption Costs. ISHPC Rakesh Kumar, Tusar Kanti Patra, Anupam Basu