Rakesh H. Patel

11 papers A* 1A 1Unranked 9

Year	Rank	Type	Title / Venue / Authors
2009	—	`conf`	Nonlinear behavior study in digital bang-bang PLL. CICC Albert Vareljian, Mohsen Moussavi, William Bereza, Walter Fergusson, Charles E. Berndt, Rakesh H. Patel
2008	—	`conf`	Session 21 - Leveraging the third Dimension. CICC Rakesh H. Patel, Michael Seningen
2007	—	`conf`	Modeling and Simulation of Noise in Closed-Loop All-Digital PLLs using Verilog-A. CICC Walter Fergusson, Rakesh H. Patel, William Bereza
2006	—	`conf`	Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs. CICC Rakesh H. Patel, William Bereza
2006	A*	`conf`	PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. DAC William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel
2005	—	`conf`	A signal integrity-based link performance simulation platform. CICC Yuming Tao, William Bereza, Rakesh H. Patel, Sergey Y. Shumarayev, Tad A. Kwasniewski
2005	—	`conf`	Design considerations for 2nd-order and 3rd-order bang-bang CDR loops. CICC Shoujun Wang, Haitao Mei, Mashkoor Baig, William Bereza, Tadeusz Kwasniewski, Rakesh H. Patel
2005	—	`conf`	Multi-protocol embedded PCS IP in a FPGA-SOC. CICC Ramanand Venkata, Vinson Chan, Binh Ton, Chong Lee, Huy Ngo, Malik Kabani, Tam Nguyen, Arch Zaliznyak, Ning Xue, Steven Shen, Michael Zheng, Michael Lai, Steve Park, Lana Chan, Divya Vijayaraghavan, John Lam, Rakesh H. Patel
2005	—	`conf`	Nanometer design intricacies. CICC Rakesh H. Patel, Paul Billig
2004	—	`conf`	Power estimation and thermal budgeting methodology for FPGAs. CICC Henry Y. Lui, Chong H. Lee, Rakesh H. Patel
2002	A	`conf`	Interconnect enhancements for a high-speed PLD architecture. FPGA Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev