Rajshekar Kalayappan

21 papers A 1B 2Misc 1Journal 12Unranked 5
YearRankTypeTitle / Venue / Authors
2026 J jnl
Dynamically Reprogrammable Runtime Monitors for Bounded-time MTL.
CoRR
Chirantan Hebballi, Akash Poptani, Amrutha Benny, Rajshekar Kalayappan, Sandeep Chandran, Ramchandra Phawade
2025 J jnl
Consequence-based Clustered Architecture.
ACM Trans. Archit. Code Optim.
Shruthi Karunakar, Rajshekar Kalayappan, Sandeep Chandran
2024 — conf
CASH: Criticality-Aware Split Hybrid L1 Data Cache.
ACM Great Lakes Symposium on VLSI
Shruthi Karunakar, Meenakshi Atkade, Akash Poptani, Rajshekar Kalayappan, Sandeep Chandran
2024 — conf
CaH2: Criticality aware Hybrid L2.
HIPCW
Shruthi Karunakar, Rajshekar Kalayappan
2024 B conf
On Decomposing Complex Test Cases for Efficient Post-silicon Validation.
ASPDAC
C. Harshitha, Sundarapalli Harikrishna, Peddakotla Rohith, Sandeep Chandran, Rajshekar Kalayappan
2024 B conf
faRM-LTL: A Domain-Specific Architecture for Flexible and Accelerated Runtime Monitoring of LTL Properties.
RV
Amrutha Benny, Sandeep Chandran, Rajshekar Kalayappan, Ramchandra Phawade, Piyush P. Kurur
2023 J jnl
Dynamic Ineffectuality-based Clustered Architectures.
CoRR
Rajshekar Kalayappan, Sandeep Chandran
2023 Misc conf
SANNA: Secure Acceleration of Neural Network Applications.
VLSID
Akash Poptani, Abhishek Mittal, Rishit Saiya, Rajshekar Kalayappan, Sandeep Chandran
2021 J jnl
A Formal Approach to Accountability in Heterogeneous Systems-on-Chip.
IEEE Trans. Dependable Secur. Comput.
Rajshekar Kalayappan, Smruti R. Sarangi
2021 J jnl
A Survey of Cache Simulators.
ACM Comput. Surv.
Hadi Brais, Rajshekar Kalayappan, Preeti Ranjan Panda
2020 J jnl
ChunkedTejas: A Chunking-based Approach to Parallelizing a Trace-Driven Architectural Simulator.
ACM Trans. Model. Comput. Simul.
Rajshekar Kalayappan, Avantika Chhabra, Smruti R. Sarangi
2018 J jnl
Providing Accountability in Heterogeneous Systems-on-Chip.
ACM Trans. Embed. Comput. Syst.
Rajshekar Kalayappan, Smruti R. Sarangi
2017 A conf
A hardware implementation of the MCAS synchronization primitive.
DATE
Srishty Patel, Rajshekar Kalayappan, Ishani Mahajan, Smruti R. Sarangi
2017 J jnl
ParTejas: A Parallel Simulator for Multicore Processors.
ACM Trans. Model. Comput. Simul.
Geetika Malhotra, Rajshekar Kalayappan, Seep Goel, Pooja Aggarwal, Abhishek Sagar, Smruti R. Sarangi
2016 J jnl
FluidCheck: A Redundant Threading-Based Approach for Reliable Execution in Manycore Processors.
ACM Trans. Archit. Code Optim.
Rajshekar Kalayappan, Smruti R. Sarangi
2016 — conf
SecCheck: A Trustworthy System with Untrusted Components.
ISVLSI
Rajshekar Kalayappan, Smruti R. Sarangi
2015 — conf
SecX: A Framework for Collecting Runtime Statistics for SoCs with Multiple Accelerators.
ISVLSI
Rajshekar Kalayappan, Smruti R. Sarangi
2015 J jnl
Tejas Simulator : Validation against Hardware.
CoRR
Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel
2015 — conf
Tejas: A java based versatile micro-architectural simulator.
PATMOS
Smruti R. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel, Eldhose Peter
2014 J jnl
Surveillance using non-stealthy sensors: A new intruder model.
Secur. Commun. Networks
Amitabha Bagchi, Rajshekar Kalayappan, Surabhi Sankhla
2013 J jnl
A survey of checker architectures.
ACM Comput. Surv.
Rajshekar Kalayappan, Smruti R. Sarangi