Rajiv V. Joshi

148 papers A* 7A 19B 1C 10Misc 13Journal 45Unranked 53

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Design Techniques for Ultra-low Power Cryogenic CMOS for Quantum Computing Applications. ISLPED Sudipto Chakraborty, Pat Rosno, John F. Bulzacchelli, David J. Frank, Rajiv V. Joshi, Daniel J. Friedman
2025	A	`conf`	Energy-Efficient Multi-Operand XOR Logic-Based CIM Accelerator using RRAM technology. ICCAD Abhairaj Singh, Konstantinos Stavrakakis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui
2024	C	`conf`	AFSRAM-CIM: Adder Free SRAM-Based Digital Computation-in-Memory for BNN. VLSI-SoC Asmae El Arrassi, Mohammad Amin Yaldagard, Xingjian Tao, Taha Shahroodi, Fouwad Jamil Mir, Yashvardhan Biyani, Manil Dev Gomony, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui
2024	—	`conf`	An Energy-Efficient High Signal Margin Analog Compute-In-Memory Architecture. LASCAS Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Jainendra Singh, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	Dynamic Detection and Mitigation of Read-disturb for Accurate Memristor-based Neural Networks. AICAS Sumit Diware, Mohammad Amin Yaldagard, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
2024	J	`jnl`	Paving the Way for Pass Disturb Free Vertical NAND Storage via A Dedicated and String-Compatible Pass Gate. CoRR Zijian Zhao, Sola Woo, Khandker Akif Aabrar, Sharadindu Gopal Kirtania, Zhouhang Jiang, Shan Deng, Yi Xiao, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Steven Soss, Sven Beyer, Rajiv V. Joshi, Scott Meninger, Mohamed Mohamed, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Vijaykrishnan Narayanan, Suman Datta, Shimeng Yu, Kai Ni
2024	J	`jnl`	Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks. IEEE Access Sumit Diware, Koteswararao Chilakala, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
2024	—	`conf`	SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology. ISQED Dinesh Kushwaha, Ashish Joshi, Abhishek Goel, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2024	C	`conf`	SRAM-Based Hybrid Analog Compute-In-memory Architecture to Enhance the Signal Margin. ISCAS Dinesh Kushwaha, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2024	—	`conf`	Variation-Aware Design Methodology for SRAM-Based Multi-Bit Analog Compute-in-Memory Architecture. NewCAS Dinesh Kushwaha, Rajiv V. Joshi, Anand Bulusu, Sudeb Dasgupta
2023	A*	`conf`	(Invited) Predictive analytics for cryogenic CMOS in future quantum computing systems. DAC Rajiv V. Joshi, Sudipto Chakraborty
2023	—	`conf`	A 115.1 TOPS/W, 12.1 TOPS/mm AICAS Abhairaj Singh, Rajendra Bishnoi, Ali Kaichouhi, Sumit Diware, Rajiv V. Joshi, Said Hamdioui
2023	J	`jnl`	A Best Balance Ratio Ordered Feature Selection Methodology for Robust and Fast Statistical Analysis of Memory Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi
2023	—	`conf`	A Fully Differential 4-Bit Analog Compute-In-Memory Architecture for Inference Application. AICAS Dinesh Kushwaha, Rajat Kohli, Jwalant Mishra, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2023	J	`jnl`	Accurate and Energy-Efficient Bit-Slicing for RRAM-Based Neural Networks. IEEE Trans. Emerg. Top. Comput. Intell. Sumit Diware, Abhairaj Singh, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
2023	Misc	`conf`	An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. VLSID Dinesh Kushwaha, Ashish Joshi, Neha Gupta, Aditya Sharma, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2023	—	`conf`	Cryogenic CMOS: design considerations for future quantum computing systems. CICC Rajiv V. Joshi, Jean-Olivier Plouchart, George Zettles, Scott Willenborg, Sudipto Chakraborty, Blake R. Johnson, Andrew Wack, Brian Allison, John Timmerwilke, Kevin Tien, Mark Yeck, Dereje Yilma, Alberto Valdes-Garcia, Daniel J. Friedman
2023	—	`conf`	Low power cryogenic RF ASICs for quantum computing. CICC David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Chris Baks, John Timmerwilke, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
2023	—	`conf`	Mapping-aware Biased Training for Accurate Memristor-based Neural Networks. AICAS Sumit Diware, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
2023	J	`jnl`	Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET. CoRR Zijian Zhao, Shan Deng, Swetaki Chatterjee, Zhouhang Jiang, Muhammad Shaffatul Islam, Yi Xiao, Yixin Xu, Scott Meninger, Mohamed Mohamed, Rajiv V. Joshi, Yogesh Singh Chauhan, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Sven Beyer, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni
2023	—	`conf`	Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture. AICAS Mohammad Amin Yaldagard, Sumit Diware, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
2023	J	`jnl`	Severity-Based Hierarchical ECG Classification Using Neural Networks. IEEE Trans. Biomed. Circuits Syst. Sumit Diware, Sudeshna Dash, Anteneh Gebregiorgis, Rajiv V. Joshi, Christos Strydis, Said Hamdioui, Rajendra Bishnoi
2022	—	`conf`	A 0.31V Vmin Cryogenic SRAM in 14 nm FinFET for Quantum Computing. VLSI Technology and Circuits Rajiv V. Joshi, John Timmerwilke, Kevin Tien, Mark Yeck, Sudipto Chakraborty
2022	C	`conf`	A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. ISCAS Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	—	`conf`	A Cryo-CMOS Low-Power Semi-Autonomous Qubit State Controller in 14nm FinFET Technology. ISSCC David J. Frank, Sudipto Chakraborty, Kevin Tien, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
2022	J	`jnl`	A Cryo-CMOS Low-Power Semi-Autonomous Transmon Qubit State Controller in 14-nm FinFET Technology. IEEE J. Solid State Circuits Sudipto Chakraborty, David J. Frank, Kevin Tien, Pat Rosno, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Devin Underwood, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Shawn D. Chambers, Scott Lekuch, Ken Inoue, Dorothy Wisnieff, Christian W. Baks, Donald S. Bethune, John Timmerwilke, Thomas Fox, Peilin Song, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
2022	A	`conf`	A Cryo-CMOS Transmon Qubit Controller and Verification with FPGA Emulation. DATE Kevin Tien, Ken Inoue, Scott Lekuch, David J. Frank, Sudipto Chakraborty, Pat Rosno, Thomas Fox, Mark Yeck, Joseph A. Glick, Raphael Robertazzi, Ray Richetta, John F. Bulzacchelli, Daniel Ramirez, Dereje Yilma, Andrew Davies, Rajiv V. Joshi, Devin Underwood, Dorothy Wisnieff, Christian W. Baks, Donald Bethune, John Timmerwilke, Blake R. Johnson, Brian P. Gaucher, Daniel J. Friedman
2022	J	`jnl`	A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs. ACM J. Emerg. Technol. Comput. Syst. Mahta Mayahinia, Abhairaj Singh, Christopher Bengel, Stefan Wiefels, Muath Abu Lebdeh, Stephan Menzel, Dirk J. Wouters, Anteneh Gebregiorgis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui
2022	A	`conf`	Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT. ITC Abhairaj Singh, Moritz Fieback, Rajendra Bishnoi, Filip Bradaric, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui
2022	J	`jnl`	An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. IEEE Trans. Circuits Syst. II Express Briefs Dinesh Kushwaha, Ashish Joshi, Chaudhry Indra Kumar, Neha Gupta, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	—	`conf`	Asymmetric Double-Gate Ferroelectric FET to Decouple the Tradeoff Between Thickness Scaling and Memory Window. VLSI Technology and Circuits Zhouhang Jiang, Yi Xiao, Swetaki Chatterjee, Halid Mulaosmanovic, Stefan Dünkel, Steven Soss, Sven Beyer, Rajiv V. Joshi, Yogesh Singh Chauhan, Hussam Amrouch, Vijaykrishnan Narayanan, Kai Ni
2022	—	`conf`	CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out. AICAS Abhairaj Singh, Mahdi Zahedi, Taha Shahroodi, Mohit Gupta, Anteneh Gebregiorgis, Manu Komalan, Rajiv V. Joshi, Francky Catthoor, Rajendra Bishnoi, Said Hamdioui
2022	J	`jnl`	Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs. IEEE Trans. Circuits Syst. II Express Briefs Neeraj Mishra, Lalit Mohan Dani, Sudipto Chakraborty, Rajiv V. Joshi, Anand Bulusu
2022	J	`jnl`	Exploring Model Stability of Deep Neural Networks for Reliable RRAM-Based In-Memory Acceleration. IEEE Trans. Computers Gokul Krishnan, Li Yang, Jingbo Sun, Jubin Hazra, Xiaocong Du, Maximilian Liehr, Zheng Li, Karsten Beckmann, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Yu Cao
2022	J	`jnl`	Ferroelectric FET based Context-Switching FPGA Enabling Dynamic Reconfiguration for Adaptive Deep Learning Machines. CoRR Yixin Xu, Zijian Zhao, Yi Xiao, Tongguang Yu, Halid Mulaosmanovic, Dominik Kleimaier, Stefan Dünkel, Sven Beyer, Xiao Gong, Rajiv V. Joshi, X. Sharon Hu, Shixian Wen, Amanda Sofie Rios, Kiran Lekkala, Laurent Itti, Eric Homan, Sumitha George, Vijaykrishnan Narayanan, Kai Ni
2022	J	`jnl`	Group LARS-Based Iterative Reweighted Least Squares Methodology for Efficient Statistical Modeling of Memory Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi, Ali Chehab
2022	J	`jnl`	Hybrid RRAM/SRAM in-Memory Computing for Robust DNN Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gokul Krishnan, Zhenyu Wang, Injune Yeo, Li Yang, Jian Meng, Maximilian Liehr, Rajiv V. Joshi, Nathaniel C. Cady, Deliang Fan, Jae-sun Seo, Yu Cao
2022	J	`jnl`	Phase Noise Analysis of Separately Driven Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. Neeraj Mishra, Anchit Proch, Lomash Chandra Acharya, Jeffrey Prinzie, Sudipto Chakraborty, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu
2022	A	`conf`	Referencing-in-Array Scheme for RRAM-based CIM Architecture. DATE Abhairaj Singh, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui
2021	—	`conf`	24.1 A 6.2 GHz Single Ended Current Sense Amplifier (CSA) Based Compileable 8T SRAM in 7nm FinFET Technology. ISSCC Alexander Fritsch, Rajiv V. Joshi, Sudipto Chakraborty, Holger Wetter, Uma Srinivasan, Matthew Hyde, Otto A. Torreiter, Michael Kugel, Dan Radko, Hyong Kim, Daniel J. Friedman
2021	C	`conf`	Low-Power Memristor-Based Computing for Edge-AI Applications. ISCAS Abhairaj Singh, Sumit Diware, Anteneh Gebregiorgis, Rajendra Bishnoi, Francky Catthoor, Rajiv V. Joshi, Said Hamdioui
2021	—	`conf`	Robust RRAM-based In-Memory Computing in Light of Model Stability. IRPS Gokul Krishnan, Jingbo Sun, Jubin Hazra, Xiaocong Du, Maximilian Liehr, Zheng Li, Karsten Beckmann, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao
2021	J	`jnl`	SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. Abhairaj Singh, Muath Abu Lebdeh, Anteneh Gebregiorgis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui
2021	—	`conf`	Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture. AICAS Sumit Diware, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
2020	A*	`conf`	Accurate Inference with Inaccurate RRAM Devices: Statistical Data, Model Transfer, and On-line Adaptation. DAC Gouranga Charan, Jubin Hazra, Karsten Beckmann, Xiaocong Du, Gokul Krishnan, Rajiv V. Joshi, Nathaniel C. Cady, Yu Cao
2019	J	`jnl`	Big vs little core for energy-efficient Hadoop computing. J. Parallel Distributed Comput. Maria Malik, Katayoun Neshatpour, Setareh Rafatirad, Rajiv V. Joshi, Tinoosh Mohsenin, Hassan Ghasemzadeh, Houman Homayoun
2019	C	`conf`	Data Imbalance Handling Approaches for Accurate Statistical Modeling and Yield Analysis of Memory Designs. ISCAS Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi
2019	J	`jnl`	Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory. IEEE Trans. Very Large Scale Integr. Syst. Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019	J	`jnl`	Hierarchical Memory System With STT-MRAM and SRAM to Support Transfer and Real-Time Reinforcement Learning in Autonomous Drones. IEEE J. Emerg. Sel. Topics Circuits Syst. Insik Yoon, Malik Aqeel Anwar, Rajiv V. Joshi, Titash Rakshit, Arijit Raychowdhury
2019	—	`conf`	Low Power Design From Moore to AI for nm Era : Invited Paper. MIXDES Rajiv V. Joshi, Matthew M. Ziegler
2019	J	`jnl`	Research From the IEEE IBM AI Compute and Emerging Technology Symposia. IEEE J. Emerg. Sel. Topics Circuits Syst. Matthew M. Ziegler, Krishnan Kailas, Xin Zhang, Rajiv V. Joshi
2019	A*	`conf`	Resilient Low Voltage Accelerators for High Energy Efficiency. HPCA Nandhini Chandramoorthy, Karthik Swaminathan, Martin Cochet, Arun Paidimarri, Schuyler Eldridge, Rajiv V. Joshi, Matthew M. Ziegler, Alper Buyuktosunoglu, Pradip Bose
2018	—	`conf`	Cascaded and resonant SRAM supply boosting for ultra-low voltage cognitive IoT applications. CICC Rajiv V. Joshi, Matthew M. Ziegler, Karthik Swaminathan, Nandhini Chandramoorthy
2018	J	`jnl`	Sparse Regression Driven Mixture Importance Sampling for Memory Design. IEEE Trans. Very Large Scale Integr. Syst. Maria Malik, Rajiv V. Joshi, Rouwaida Kanj, Shupeng Sun, Houman Homayoun, Tong Li
2017	J	`jnl`	A Low Voltage SRAM Using Resonant Supply Boosting. IEEE J. Solid State Circuits Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter
2017	J	`jnl`	Distributed In-Memory Computing on Binary RRAM Crossbar. ACM J. Emerg. Technol. Comput. Syst. Leibin Ni, Hantao Huang, Zichuan Liu, Rajiv V. Joshi, Hao Yu
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017	J	`jnl`	Editorial. IEEE Trans. Very Large Scale Integr. Syst. Krishnendu Chakrabarty, Massimo Alioto, Rajiv V. Joshi
2017	—	`conf`	Programmable supply boosting techniques for near threshold and wide operating voltage SRAM. CICC Rajiv V. Joshi, Matthew M. Ziegler
2017	—	`conf`	Regularized logistic regression for fast importance sampling based SRAM yield analysis. ISQED Lama Shaer, Rouwaida Kanj, Rajiv V. Joshi, Maria Malik, Ali Chehab
2017	—	`conf`	Session 5 - Memory for emerging applications. CICC Muhammad M. Khellah, Rajiv V. Joshi
2017	C	`conf`	Very Low Voltage (VLV) Design. ICCD Ramon Bertran, Pradip Bose, David M. Brooks, Jeff Burns, Alper Buyuktosunoglu, Nandhini Chandramoorthy, Eric Cheng, Martin Cochet, Schuyler Eldridge, Daniel J. Friedman, Hans M. Jacobson, Rajiv V. Joshi, Subhasish Mitra, Robert K. Montoye, Arun Paidimarri, Pritish Parida, Kevin Skadron, Mircea Stan, Karthik Swaminathan, Augusto Vega, Swagath Venkataramani, Christos Vezyrtzis, Gu-Yeon Wei, John-David Wellman, Matthew M. Ziegler
2017	—	`conf`	Yield and energy tradeoffs of an NVLatch design using radial sampling. ICICDT Adam Issa, Rouwaida Kanj, Ali Chehab, Rajiv V. Joshi
2016	J	`jnl`	A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM. IEEE Trans. Very Large Scale Integr. Syst. Rajiv V. Joshi, Sudesh Saroop, Rouwaida Kanj, Yang Liu, Weike Wang, Carl Radens, Yue Tan, Karthik Yogendra
2016	C	`conf`	Big biomedical image processing hardware acceleration: A case study for K-means and image filtering. ISCAS Katayoun Neshatpour, Arezou Koohi, Farnoud Farahmand, Rajiv V. Joshi, Setareh Rafatirad, Avesta Sasan, Houman Homayoun
2016	B	`conf`	Characterizing Hadoop applications on microservers for performance and energy efficiency optimizations. ISPASS Maria Malik, Avesta Sasan, Rajiv V. Joshi, Setareh Rafatirah, Houman Homayoun
2016	—	`conf`	Efficient analog circuit optimization using sparse regression and error margining. ISQED Mohamed Baker Alawieh, Fa Wang, Rouwaida Kanj, Xin Li, Rajiv V. Joshi
2016	J	`jnl`	Guest Editorial Emerging Memories - Technology, Architecture and Applications (First Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li
2016	J	`jnl`	Guest Editorial Emerging Memories - Technology, Architecture and Applications (Second Issue). IEEE J. Emerg. Sel. Topics Circuits Syst. Swaroop Ghosh, Rajiv V. Joshi, Dinesh Somasekhar, Xin Li
2016	J	`jnl`	Overview of Circuits, Systems, and Applications of Spintronics. IEEE J. Emerg. Sel. Topics Circuits Syst. Swaroop Ghosh, Anirudh Iyengar, Seyedhamidreza Motaman, Rekha Govindaraj, Jae-Won Jang, Jinil Chung, Jongsun Park, Xin Li, Rajiv V. Joshi, Dinesh Somasekhar
2015	—	`conf`	14nm FinFET based supply voltage boosting techniques for extreme low Vmin operation. VLSIC Rajiv V. Joshi, Matthew M. Ziegler, Holger Wetter, C. Wandel, Herschel A. Ainspan
2015	J	`jnl`	Corrections to "Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction". IEEE Trans. Very Large Scale Integr. Syst. Rajiv V. Joshi, Rouwaida Kanj
2015	J	`jnl`	Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction. IEEE Trans. Very Large Scale Integr. Syst. Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh
2014	A*	`conf`	A New Field-assisted Access Scheme of STT-RAM with Self-reference Capability. DAC Enes Eken, Yaojun Zhang, Wujie Wen, Rajiv V. Joshi, Hai Li, Yiran Chen
2014	—	`conf`	Design technology co-optimization for 10 nm and beyond. CICC Takamaro Kikkawa, Rajiv V. Joshi
2014	—	`conf`	Impact of FinFET technology for power gating in nano-scale design. ISQED Keunwoo Kim, Rouwaida Kanj, Rajiv V. Joshi
2014	—	`conf`	Robust bias temperature instability refresh design and methodology for memory cell recovery. ICICDT Gerard Touma, Rouwaida Kanj, Rajiv V. Joshi, Ayman I. Kayssi, Ali Chehab
2014	—	`conf`	Statistical methodology for modeling non-IID memory fails events. ISQED Sabine Francis, Rouwaida Kanj, Rajiv V. Joshi, Ayman I. Kayssi, Ali Chehab
2014	—	`conf`	TCAD structure synthesis and capacitance extraction of a voltage-controlled oscillator using automated layout-to-device synthesis methodology. CICC Debajit Bhattacharya, Rajiv V. Joshi, Herschel A. Ainspan, Ninad D. Sathaye, Mohit Bajaj, Suresh Gundapaneni, Niraj K. Jha
2014	—	`conf`	The resilience wall: Cross-layer solution strategies. VLSI-DAT Subhasish Mitra, Pradip Bose, Eric Cheng, Chen-Yong Cher, Hyungmin Cho, Rajiv V. Joshi, Young Moon Kim, Charles R. Lefurgy, Yanjing Li, Kenneth P. Rodbell, Kevin Skadron, James H. Stathis, Lukasz G. Szafaryn
2013	J	`jnl`	3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits. IEEE Trans. Very Large Scale Integr. Syst. Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha
2013	J	`jnl`	Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha
2013	Misc	`conf`	Hardware-corroborated Variability-Aware SRAM Methodology. VLSI Design Rajiv V. Joshi, Rouwaida Kanj, S. Butt, Emrah Acar, Dallas Lea, D. Sciacca
2013	—	`conf`	Welcome to ISQED 2013. ISQED Mark M. Budnik, Rasit Onur Topaloglu, Pallab Chatterjee, Keith A. Bowman, Kamesh V. Gadepally, Paul Wesling, Syed M. Alam, Rajiv V. Joshi
2012	—	`conf`	A novel sample reuse methodology for fast statistical simulations with applications to manufacturing variability. ISQED Rouwaida Kanj, Rajiv V. Joshi
2012	A	`conf`	A thermal and process variation aware MTJ switching model and its applications in soft error analysis. ICCAD Peiyuan Wang, Wei Zhang, Rajiv V. Joshi, Rouwaida Kanj, Yiran Chen
2012	—	`conf`	Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. VLSIC John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver
2012	A*	`conf`	Yield estimation via multi-cones. DAC Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jerry Hayes, Sani R. Nassif
2011	J	`jnl`	A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design. IEEE Trans. Very Large Scale Integr. Syst. Rajiv V. Joshi, Rouwaida Kanj, Vinod Ramadurai
2011	—	`conf`	A Tutorial on Enhancing the Level-of-Learning through ICT-Enabled Teaching in Engineering Education. T4E J. Sujatha, Rajshri Jobanputra, Rajiv V. Joshi
2011	A	`conf`	Accelerated statistical simulation via on-demand Hermite spline interpolations. ICCAD Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif
2011	J	`jnl`	The Impact of Statistical Leakage Models on Design Yield Estimation. VLSI Design Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
2011	A	`conf`	Universal statistical cure for predicting memory loss. ICCAD Rajiv V. Joshi, Rouwaida Kanj, Peiyuan Wang, Hai Li
2010	Misc	`conf`	FinFET SRAM Design. VLSI Design Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj
2010	A	`conf`	Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. ISLPED Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
2010	J	`jnl`	The Dawn of Predictive Chip Yield Design: Along and Beyond the Memory Lane. IEEE Des. Test Comput. Rajiv V. Joshi, Rouwaida Kanj, Anthony Pelella, Arthur Tuminaro, Yuen H. Chan
2010	—	`conf`	Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test. ISQED Jeanne Bickford, Nazmul Habib, John Goss, Robert McMahon, Rajiv V. Joshi, Rouwaida Kanj
2009	A	`conf`	An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. ICCAD Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James D. Warnock, Sani R. Nassif
2009	J	`jnl`	Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics. IEEE J. Solid State Circuits Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Yue Tan
2009	—	`conf`	Statistical yield analysis of silicon-on-insulator embedded DRAM. ISQED Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka
2009	—	`conf`	The impact of BEOL lithography effects on the SRAM cell performance and yield. ISQED Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi
2008	—	`conf`	A Root-Finding Method for Assessing SRAM Stability. ISQED Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif
2008	A	`conf`	SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. ISLPED Rouwaida Kanj, Rajiv V. Joshi, Zhuo Li, Jente B. Kuang, Hung C. Ngo, Nancy Ying Zhou, Weiping Shi, Sani R. Nassif
2008	—	`conf`	Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. ISQED Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif
2008	—	`conf`	Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. ISQED Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang
2007	—	`conf`	A Disturb Decoupled Column Select 8T SRAM Cell. CICC Vinod Ramadurai, Rajiv V. Joshi, Rouwaida Kanj
2007	Misc	`conf`	A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. VLSI Design Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang
2007	A	`conf`	A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. ISLPED Rajiv V. Joshi, Rouwaida Kanj, Keunwoo Kim, Richard Q. Williams, Ching-Te Chuang
2007	J	`jnl`	Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectron. J. Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
2007	—	`conf`	Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. ISQED Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif
2006	—	`conf`	A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. ISSCC John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr
2006	A*	`conf`	A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. DAC Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
2006	A*	`conf`	Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. DAC Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
2006	Misc	`conf`	Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. VLSI Design Ruchir Puri, Tanay Karnik, Rajiv V. Joshi
2006	—	`conf`	Tutorial 1: Emerging Technologies for VLSI Design. ISQED Rajiv V. Joshi, Kaustav Banerjee, André DeHon
2005	C	`conf`	A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction. ICCD Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, Jethro C. Law, Rajiv V. Joshi
2005	—	`conf`	A novel circuit topology for generating and validating digitally sense amplifier differentials for bulk and SOI. ESSCIRC Rajiv V. Joshi, Yuen H. Chan
2005	—	`conf`	Design of sub-90nm Circuits and Design Methodologies. ISQED Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi
2005	Misc	`conf`	Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. VLSI Design Rajiv V. Joshi, S. S. Kang, N. Zamdmar, Anda Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez
2005	—	`conf`	Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
2004	Misc	`conf`	A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. VLSI Design Rajiv V. Joshi, K. Kroell, Ching-Te Chuang
2004	A	`conf`	Nanoscale CMOS circuit leakage power reduction by double-gate device. ISLPED Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang
2004	A	`ed.`	Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004 ISLPED Rajiv V. Joshi, Kiyoung Choi, Vivek Tiwari, Kaushik Roy
2004	—	`conf`	Variability analysis for sub-100 nm PD/SOI CMOS SRAM cell. ESSCIRC Rajiv V. Joshi, Saibal Mukhopadhyay, Donald W. Plass, Yuen H. Chan, Ching-Te Chuang, Anirudh Devgan
2003	—	`conf`	Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. ISQED Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim
2003	A	`conf`	Design and CAD Challenges in sub-90nm CMOS Technologies. ICCAD Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri
2003	Misc	`conf`	Design of Deep Sub-Micron CMOS Circuits. VLSI Design Rajiv V. Joshi, Kaushik Roy
2003	J	`jnl`	Influence and model of gate oxide breakdown on CMOS inverters. Microelectron. Reliab. Rosana Rodríguez, James H. Stathis, Barry P. Linder, Rajiv V. Joshi, Ching-Te Chuang
2003	—	`conf`	New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology. ESSCIRC Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown
2003	A	`conf`	New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. ISLPED Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown
2003	J	`jnl`	PD/SOI SRAM performance in presence of gate-to-body tunneling current. IEEE Trans. Very Large Scale Integr. Syst. Rajiv V. Joshi, Ching-Te Chuang, Samuel K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi
2003	J	`jnl`	Preface. IBM J. Res. Dev. E. N. Elnozahy, Rajiv V. Joshi
2003	A	`conf`	Strained-si devices and circuits for low-power applications. ISLPED Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang
2003	—	`conf`	Three dimensional CMOS devices and integrated circuits. CICC Mei-Kei Ieong, Kathryn W. Guarini, Victor Chan, Kerry Bernstein, Rajiv V. Joshi, Jakub Kedzierski, Wilfred Haensch
2002	J	`jnl`	Analysis of the effect of the gate oxide breakdown on SRAM stability. Microelectron. Reliab. Rosana Rodríguez, James H. Stathis, Barry P. Linder, Steven P. Kowalczyk, Ching-Te Chuang, Rajiv V. Joshi, Gregory A. Northrop, Kerry Bernstein, Azeez J. Bhavnagarwala, Salvatore Lombardo
2001	Misc	`conf`	Design Of Provably Correct Storage Arrays. VLSI Design Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
2001	Misc	`conf`	IBM's Blue Logic Design Methodology-Circuits and Physical Design. VLSI Design Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty
2001	A	`conf`	Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi
2001	—	`conf`	SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang
2000	A	`conf`	"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang
2000	Misc	`conf`	A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang
2000	J	`jnl`	A scannable pulse-to-static conversion register array for self-timed circuits. IEEE J. Solid State Circuits Wei Hwang, Rajiv V. Joshi, George Gristede
1999	J	`jnl`	A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file. IEEE J. Solid State Circuits Wei Hwang, Rajiv V. Joshi, Walter H. Henkels
1999	Misc	`conf`	Design Considerations and Implementation of a High Performance Dynamic Register File. VLSI Design Rajiv V. Joshi, Wei Hwang
1998	Misc	`conf`	Designing a Testable System on a Chip. VTS Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin Stawiasz
1997	C	`conf`	A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. ICCD Wei Hwang, Rajiv V. Joshi, Walter H. Henkels
1997	C	`conf`	Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi
1991	J	`jnl`	A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture. IEEE J. Solid State Circuits Terry I. Chappell, Barbara A. Chappell, Stanley E. Schuster, James W. Allan, Stephen P. Klepner, Rajiv V. Joshi, Robert L. Franch