Rajiv A. Ravindran

12 papers A* 1A 3B 1Misc 2Journal 3Unranked 1
YearRankTypeTitle / Venue / Authors
2007 B conf
Compiler-managed partitioned data caches for low power.
LCTES
Rajiv A. Ravindran, Michael L. Chu, Scott A. Mahlke
2007 A* conf
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures.
MICRO
Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlke
2007 — —
Hardware/software techniques for memory power optimizations in embedded processors.
Rajiv A. Ravindran
2005 A conf
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache.
CGO
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh S. Dasika, Eric D. Marsman, Robert M. Senger, Scott A. Mahlke, Richard B. Brown
2005 J jnl
Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor.
IEEE Trans. Computers
Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown
2004 J jnl
Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors.
IEEE Micro
Michael L. Chu, Kevin Fan, Rajiv A. Ravindran, Scott A. Mahlke
2004 A conf
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths.
CGO
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv A. Ravindran, Nathan Clark, Scott A. Mahlke
2003 Misc conf
Increasing the number of effective registers in a low-power processor using a windowed register file.
CASES
Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown
2003 — conf
Systematic Register Bypass Customization for Application-Specific Processors.
ASAP
Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke
2001 J jnl
Bitwidth cognizant architecture synthesis of custom hardwareaccelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood
2001 A conf
Retargetable Cache Simulation Using High Level Processor Models.
ACSAC
Rajiv A. Ravindran, Rajat Moona
2001 Misc conf
Retargetable Program Profiling Using High Level Processor Models.
HiPC
Rajiv A. Ravindran, Rajat Moona