Rajit Manohar - RankMe

137 papers A* 8A 12B 7C 3Misc 1Journal 37Unranked 68

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Accio: Rethinking OS-Architecture Co-Design for Next-Gen I/O. NINeS Amirmohammad Nazari, Rajit Manohar, Robert Soulé
2026	J	`jnl`	Maelstrom: A Logic Synthesis Technique for Asynchronous Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Karthi Srinivasan, Rajit Manohar
2025	—	`conf`	Asynchronous, event-driven readout for large-scale imaging devices. ASYNC Prafull Purohit, Rajit Manohar
2025	—	`conf`	Automated Decomposition of Concurrent Programs for Asynchronous Logic Synthesis. ASYNC Karthi Srinivasan, Rajit Manohar
2025	B	`conf`	Dataflow-Specific Algorithms for Resource-Constrained Scheduling and Memory Design. SPAA Abhishek Bhattacharjee, Quanquan C. Liu, Rajit Manohar, Raghavendra Pradyumna Pothukuchi, Muhammed Ugur
2025	A*	`conf`	PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis. DAC Rui Li, Lincoln Berkley, Rajit Manohar
2025	A	`conf`	PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level Synthesis. FPGA Rui Li, Rajit Manohar
2025	—	`conf`	Translating General Slack Elastic Programs into Dataflow Circuits. ASYNC Xiayuan Wen, Rui Li, Rajit Manohar
2024	A	`conf`	Designing an Energy-Efficient Fully-Asynchronous Deep Learning Convolution Engine. DATE Mattia Vezzoli, Lukas Nel, Kshitij Bhardwaj, Rajit Manohar, Maya B. Gokhale
2024	J	`jnl`	Distributed Brain-Computer Interfacing With a Networked Multiaccelerator Architecture. IEEE Micro Raghavendra Pradyumna Pothukuchi, Karthik Sriram, Michal Gerasimiuk, Muhammed Ugur, Rajit Manohar, Anurag Khandelwal, Abhishek Bhattacharjee
2024	—	`conf`	High Quality Circuit-Based 3-SAT Mappings for Oscillator Ising Machines. UCNC Venkata Pavan Sumanth Sikhakollu, Shreesha Sreedhara, Rajit Manohar, Alan Mishchenko, Jaijeet Roychowdhury
2024	J	`jnl`	Neuro-Symbolic Computing: Advancements and Challenges in Hardware-Software Co-Design. IEEE Trans. Circuits Syst. II Express Briefs Xiaoxuan Yang, Zhangyang Wang, X. Sharon Hu, Chris H. Kim, Shimeng Yu, Miroslav Pajic, Rajit Manohar, Yiran Chen, Hai Helen Li
2024	—	`conf`	Split gRPC: An Isolation Architecture for RPC Software Stacks. APSys Esteban Ramos, Robert Soulé, Peter Alvaro, Pietro Bressana, Edmund Chen, Uri Cummings, Rui Li, James Tsai, Rajit Manohar
2023	J	`jnl`	A Multi-Site Accelerator-Rich Processing Fabric for Scalable Brain-Computer Interfacing. CoRR Karthik Sriram, Raghavendra Pradyumna Pothukuchi, Michal Gerasimiuk, Oliver Ye, Muhammed Ugur, Rajit Manohar, Anurag Khandelwal, Abhishek Bhattacharjee
2023	—	`conf`	An Efficient Data Structure for Sparse Bit-Vectors with Applications in Neuromorphic Computing. ASYNC Prafull Purohit, Johannes Leugering, Rajit Manohar
2023	J	`jnl`	FPIM: Field-Programmable Ising Machines for Solving SAT. CoRR Thomas Jagielski, Rajit Manohar, Jaijeet Roychowdhury
2023	J	`jnl`	HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces. IEEE Micro Karthik Sriram, Ioannis Karageorgos, Xiayuan Wen, Ján Veselý, Nick Lindsay, Michael Wu, Lenny Khazan, Raghavendra Pradyumna Pothukuchi, Rajit Manohar, Abhishek Bhattacharjee
2023	J	`jnl`	NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. CoRR Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David M. Harris, Rajit Manohar, Pinaki Mazumder, Larry T. Pileggi, James E. Stine
2023	J	`jnl`	NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking. CoRR Jason Yik, Soikat Hasan Ahmed, Zergham Ahmed, Brian Anderson, Andreas G. Andreou, Chiara Bartolozzi, Arindam Basu, Douwe den Blanken, Petrut Bogdan, Sander M. Bohté, Younes Bouhadjar, Sonia M. Buckley, Gert Cauwenberghs, Federico Corradi, Guido de Croon, Andreea Danielescu, Anurag Reddy Daram, Mike Davies, Yigit Demirag, Jason Eshraghian, Jeremy Forest, Steve B. Furber, P. Michael Furlong, Aditya Gilra, Giacomo Indiveri, Siddharth Joshi, Vedant Karia, Lyes Khacef, James C. Knight, Laura Kriener, Rajkumar Kubendran, Dhireesha Kudithipudi, Gregor Lenz, Rajit Manohar, Christian Mayr, Konstantinos P. Michmizos, Dylan R. Muir, Emre Neftci, Thomas Nowotny, Fabrizio Ottati, Ayça Özcelikkale, Noah Pacik-Nelson, Priyadarshini Panda, Pao-Sheng Sun, Melika Payvand, Christian Pehle, Mihai A. Petrovici, Christoph Posch, Alpha Renner, Yulia Sandamirskaya, Clemens JS Schaefer, André van Schaik, Johannes Schemmel, Catherine D. Schuman, Jae-sun Seo, Sumit Bam Shrestha, Manolis Sifalakis, Amos Sironi, Kenneth Michael Stewart, Terrence C. Stewart, Philipp Stratmann, Guangzhi Tang, Jonathan Timcheck, Marian Verhelst, Craig M. Vineyard, Bernhard Vogginger, Amirreza Yousefzadeh, Biyan Zhou, Fatima Tuz Zohora, Charlotte Frenkel, Vijay Janapa Reddi
2023	—	`conf`	Opportunistic Mutual Exclusion. ASYNC Karthi Srinivasan, Yoram Moses, Rajit Manohar
2023	J	`jnl`	Opportunistic Mutual Exclusion. CoRR Karthi Srinivasan, Yoram Moses, Rajit Manohar
2023	A*	`conf`	SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing. ISCA Karthik Sriram, Raghavendra Pradyumna Pothukuchi, Michal Gerasimiuk, Muhammed Ugur, Oliver Ye, Rajit Manohar, Anurag Khandelwal, Abhishek Bhattacharjee
2023	—	`conf`	Timed Signalling Processes. ASYNC Rajit Manohar, Yoram Moses
2023	—	`conf`	Verification-Driven Design for Asynchronous VLSI. ASYNC Xiang Wu, Rajit Manohar
2022	—	`conf`	A Simple, Fast, and GPU-friendly Steiner-Tree Heuristic. IPDPS Workshops Alex Fallin, Aarti Kothari, Jiayuan He, Christopher Yanez, Keshav Pingali, Rajit Manohar, Martin Burtscher
2022	J	`jnl`	General Approach to Asynchronous Circuits Simulation Using Synchronous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ruslan Dashkin, Rajit Manohar
2022	—	`conf`	HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces. HCS Abhishek Bhattacharjee, Rajit Manohar
2022	—	`conf`	Hardware/software Co-design for Neuromorphic Systems. CICC Rajit Manohar
2022	—	`conf`	SPRoute 2.0: A detailed-routability-driven deterministic parallel global router with soft capacity. ASP-DAC Jiayuan He, Udit Agarwal, Yihang Yang, Rajit Manohar, Keshav Pingali
2021	J	`jnl`	An Open-Source EDA Flow for Asynchronous Logic. IEEE Des. Test Samira Ataei, Wenmian Hua, Yihang Yang, Rajit Manohar, Yi-Shan Lu, Jiayuan He, Sepideh Maleki, Keshav Pingali
2021	J	`jnl`	Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces. IEEE Micro Ioannis Karageorgos, Karthik Sriram, Ján Veselý, Nick Lindsay, Xiayuan Wen, Michael Wu, Marc Powell, David A. Borton, Rajit Manohar, Abhishek Bhattacharjee
2021	—	`conf`	Fluid: An Asynchronous High-level Synthesis Tool for Complex Program Structures. ASYNC Rui Li, Lincoln Berkley, Yihang Yang, Rajit Manohar
2021	—	`conf`	Hierarchical Token Rings for Address-Event Encoding. ASYNC Prafull Purohit, Rajit Manohar
2021	A	`conf`	Zerializer: towards zero-copy serialization. HotOS Adam Wolnikowski, Stephen Ibanez, Jonathan Stone, Changhoon Kim, Rajit Manohar, Robert Soulé
2020	J	`jnl`	A Systematic Approach for Arbitration Expressions. IEEE Trans. Circuits Syst. Ned Bingham, Rajit Manohar
2020	—	`conf`	Cyclone: A Static Timing and Power Engine for Asynchronous Circuits. ASYNC Wenmian Hua, Yi-Shan Lu, Keshav Pingali, Rajit Manohar
2020	A	`conf`	Dali: A Gridded Cell Placement Flow. ICCAD Yihang Yang, Jiayuan He, Rajit Manohar
2020	J	`jnl`	Exact Timing Analysis for Asynchronous Circuits With Multiple Periods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Rajit Manohar
2020	J	`jnl`	HABIT: Hardware-Assisted Bluetooth-based Infection Tracking. IACR Cryptol. ePrint Arch. Nathan Manohar, Peter Manohar, Rajit Manohar
2020	A*	`conf`	Hardware-Software Co-Design for Brain-Computer Interfaces. ISCA Ioannis Karageorgos, Karthik Sriram, Ján Veselý, Michael Wu, Marc Powell, David A. Borton, Rajit Manohar, Abhishek Bhattacharjee
2020	—	`conf`	Shared-Staticizer for Area-Efficient Asynchronous Circuits. ASYNC Samira Ataei, Rajit Manohar
2019	—	`conf`	AMC: An Asynchronous Memory Compiler. ASYNC Samira Ataei, Rajit Manohar
2019	—	`conf`	Asynchronous Signalling Processes. ASYNC Rajit Manohar, Yoram Moses
2019	J	`jnl`	Braindrop: A Mixed-Signal Neuromorphic Architecture With a Dynamical Systems-Based Programming Model. Proc. IEEE Alexander Neckar, Sam Fok, Ben Varkey Benjamin, Terrence C. Stewart, Nick N. Oza, Aaron R. Voelker, Chris Eliasmith, Rajit Manohar, Kwabena Boahen
2019	J	`jnl`	Operation-Dependent Frequency Scaling Using Desynchronization. IEEE Trans. Very Large Scale Integr. Syst. Nitish Kumar Srivastava, Rajit Manohar
2019	J	`jnl`	QDI Constant-Time Counters. IEEE Trans. Very Large Scale Integr. Syst. Ned Bingham, Rajit Manohar
2019	A	`conf`	SPRoute: A Scalable Parallel Negotiation-based Global Router. ICCAD Jiayuan He, Martin Burtscher, Rajit Manohar, Keshav Pingali
2019	J	`jnl`	Self-Timed Adaptive Digit-Serial Addition. IEEE Trans. Very Large Scale Integr. Syst. Ned Bingham, Rajit Manohar
2018	J	`jnl`	A Continuous-Time Digital IIR Filter With Signal-Derived Timing and Fully Agile Power Consumption. IEEE J. Solid State Circuits Yu Chen, Xiaoyang Zhang, Yong Lian, Rajit Manohar, Yannis P. Tsividis
2018	J	`jnl`	Exact Timing Analysis for Asynchronous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wenmian Hua, Rajit Manohar
2018	J	`jnl`	The Impact of On-chip Communication on Memory Technologies for Neuromorphic Systems. CoRR Saber Moradi, Rajit Manohar
2017	A	`conf`	Accelerating Face Detection on Programmable SoC Using C-Based Synthesis. FPGA Nitish Kumar Srivastava, Steve Dai, Rajit Manohar, Zhiru Zhang
2017	B	`conf`	DeepRecon: Dynamically reconfigurable architecture for accelerating deep neural networks. IJCNN Tayyar Rzayev, Saber Moradi, David H. Albonesi, Rajit Manohar
2017	—	`conf`	Design of tunable digital delay cells. CICC Yu Chen, Rajit Manohar, Yannis P. Tsividis
2017	J	`jnl`	Energy-efficient Hybrid CMOS-NEMS LIF Neuron Circuit in 28 nm CMOS Process. CoRR Saber Moradi, Sunil A. Bhave, Rajit Manohar
2017	—	`conf`	Energy-efficient hybrid CMOS-NEMS LIF neuron circuit in 28 nm CMOS process. SSCI Saber Moradi, Sunil A. Bhave, Rajit Manohar
2017	A*	`conf`	On Using Time Without Clocks via Zigzag Causality. PODC Asa Dan, Rajit Manohar, Yoram Moses
2017	J	`jnl`	On Using Time Without Clocks via Zigzag Causality. CoRR Asa Dan, Rajit Manohar, Yoram Moses
2017	—	`conf`	The Eventual C-Element Theorem for Delay-Insensitive Asynchronous Circuits. ASYNC Rajit Manohar, Yoram Moses
2017	B	`conf`	Toolbox for exploration of energy-efficient event processors for human-computer interaction. ISPASS Tayyar Rzayev, David H. Albonesi, François Guimbretière, Rajit Manohar, Jaeyeon Kihm
2016	—	`conf`	Gradual Synchronization. ASYNC Sandra J. Jackson, Rajit Manohar
2015	—	`conf`	AES Hardware-Software Co-design in WSN. ASYNC Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar
2015	—	`conf`	Analyzing Isochronic Forks with Potential Causality. ASYNC Rajit Manohar, Yoram Moses
2015	—	`conf`	Automatic obfuscated cell layout for trusted split-foundry design. HOST Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar
2015	J	`jnl`	Comparing Stochastic and Deterministic Computing. IEEE Comput. Archit. Lett. Rajit Manohar
2015	C	`conf`	Design of a QDI asynchronous AER serializer/deserializer link in 180nm for event-based sensors for robotic applications. ISCAS Giovanni Rovere, Chiara Bartolozzi, Nabil Imam, Rajit Manohar
2015	A*	`conf`	Preventing glitches and short circuits in high-level self-timed chip specifications. PLDI Stephen Longfield Jr., Brittany Nkounkou, Rajit Manohar, Ross Tate
2015	—	`conf`	Timing Driven Placement for Quasi Delay-Insensitive Circuits. ASYNC Robert Karmazin, Stephen Longfield Jr., Carlos Tadeo Ortega Otero, Rajit Manohar
2015	J	`jnl`	TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Filipp Akopyan, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John V. Arthur, Paul Merolla, Nabil Imam, Yutaka Y. Nakamura, Pallab Datta, Gi-Joon Nam, Brian Taba, Michael P. Beakes, Bernard Brezzo, Jente B. Kuang, Rajit Manohar, William P. Risk, Bryan L. Jackson, Dharmendra S. Modha
2014	J	`jnl`	An asymmetric dual-processor architecture for low-power information appliances. ACM Trans. Embed. Comput. Syst. François Guimbretière, Shenwei Liu, Han Wang, Rajit Manohar
2014	—	`conf`	Low Power Asynchronous VLSI with NEM Relays. ASYNC Benjamin Z. Tang, Sunil A. Bhave, Rajit Manohar
2014	A	`conf`	Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution. SC Andrew S. Cassidy, Rodrigo Alvarez-Icaza, Filipp Akopyan, Jun Sawada, John V. Arthur, Paul Merolla, Pallab Datta, Marc González Tallada, Brian Taba, Alexander Andreopoulos, Arnon Amir, Steven K. Esser, Jeff Kusnitz, Rathinakumar Appuswamy, Chuck Haymes, Bernard Brezzo, Roger Moussalli, Ralph Bellofatto, Christian W. Baks, Michael Mastro, Kai Schleupen, Charles E. Cox, Ken Inoue, Steven E. Millman, Nabil Imam, Emmett McQuinn, Yutaka Y. Nakamura, Ivan Vo, Chen Guok, Don Nguyen, Scott Lekuch, Sameh W. Asaad, Daniel J. Friedman, Bryan L. Jackson, Myron Flickner, William P. Risk, Rajit Manohar, Dharmendra S. Modha
2014	A	`conf`	Removing concurrency for rapid functional verification. ICCAD Stephen Longfield Jr., Rajit Manohar
2014	—	`conf`	ULSNAP: An ultra-low power event-driven microcontroller for sensor network nodes. ISQED Carlos Tadeo Ortega Otero, Jonathan Tse, Robert Karmazin, Benjamin Hill, Rajit Manohar
2014	A*	`conf`	Using asymmetric cores to reduce power consumption for interactive devices with bi-stable displays. CHI Jaeyeon Kihm, François Guimbretière, Julia Karl, Rajit Manohar
2013	—	`conf`	A Bit of Analysis on Self-Timed Single-Bit On-Chip Links. ASYNC Jonathan Tse, Benjamin Hill, Rajit Manohar
2013	—	`conf`	A memory-efficient routing method for large-scale spiking neural networks. ECCTD Saber Moradi, Nabil Imam, Rajit Manohar, Giacomo Indiveri
2013	—	`conf`	A split-foundry asynchronous FPGA. CICC Benjamin Hill, Robert Karmazin, Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar
2013	—	`conf`	Inverting Martin Synthesis for Verification. ASYNC Stephen Longfield Jr., Rajit Manohar
2013	B	`conf`	Neural spiking dynamics in asynchronous digital circuits. IJCNN Nabil Imam, Kyle Wecker, Jonathan Tse, Robert Karmazin, Rajit Manohar
2013	—	`conf`	cellTK: Automated Layout for Asynchronous Circuits with Nonstandard Cells. ASYNC Robert Karmazin, Carlos Tadeo Ortega Otero, Rajit Manohar
2012	—	`conf`	A Digital Neurosynaptic Core Using Event-Driven QDI Circuits. ASYNC Nabil Imam, Filipp Akopyan, John V. Arthur, Paul Merolla, Rajit Manohar, Dharmendra S. Modha
2012	—	`conf`	A Low Power Asynchronous GPS Baseband Processor. ASYNC Benjamin Z. Tang, Stephen Longfield Jr., Sunil A. Bhave, Rajit Manohar
2012	—	`conf`	An Asynchronous Floating-Point Multiplier. ASYNC Basit Riaz Sheikh, Rajit Manohar
2012	B	`conf`	Building block of a programmable neuromorphic substrate: A digital neurosynaptic core. IJCNN John V. Arthur, Paul Merolla, Filipp Akopyan, Rodrigo Alvarez-Icaza, Andrew Cassidy, Shyamal Chandra, Steven K. Esser, Nabil Imam, William P. Risk, Daniel Ben Dayan Rubin, Rajit Manohar, Dharmendra S. Modha
2012	J	`jnl`	Dynamic electrothermal simulation of three-dimensional integrated circuits using standard cell macromodels. IET Circuits Devices Syst. Shivam Priyadarshi, T. Robert Harris, Samson Melamed, Carlos Tadeo Ortega Otero, Nikhil Kriplani, Carlos E. Christoffersen, Rajit Manohar, Steven R. Dooley, W. Rhett Davis, Paul D. Franzon, Michael B. Steer
2011	—	`conf`	A digital neurosynaptic core using embedded crossbar memory with 45pJ per spike in 45nm. CICC Paul Merolla, John V. Arthur, Filipp Akopyan, Nabil Imam, Rajit Manohar, Dharmendra S. Modha
2011	—	`conf`	Address-Event Communication Using Token-Ring Mutual Exclusion. ASYNC Nabil Imam, Rajit Manohar
2011	J	`jnl`	Energy-Efficient Pipeline Templates for High-Performance Asynchronous Circuits. ACM J. Emerg. Technol. Comput. Syst. Basit Riaz Sheikh, Rajit Manohar
2010	—	`conf`	An Asynchronous FPGA with Two-Phase Enable-Scaled Routing. ASYNC Christopher LaFrieda, Benjamin Hill, Rajit Manohar
2010	—	`conf`	An Operand-Optimized Asynchronous IEEE 754 Double-Precision Floating-Point Adder. ASYNC Basit Riaz Sheikh, Rajit Manohar
2010	—	`conf`	Static Power Reduction Techniques for Asynchronous Circuits. ASYNC Carlos Tadeo Ortega Otero, Jonathan Tse, Rajit Manohar
2009	—	`conf`	Reducing Power Consumption with Relaxed Quasi Delay-Insensitive Circuits. ASYNC Christopher LaFrieda, Rajit Manohar
2008	—	`conf`	Variability in 3-D integrated circuits. CICC Filipp Akopyan, Carlos Tadeo Ortega Otero, David Fang, Sandra J. Jackson, Rajit Manohar
2007	—	`conf`	Analog and asynchronous variation-aware circuits. ICECS Alyssa B. Apsel, Rajit Manohar, Alain J. Martin
2007	J	`jnl`	Resource-Constrained Signal Processing, Communications, and Networking [From the Guest Editors]. IEEE Signal Process. Mag. Qing Zhao, Rajit Manohar, Robert J. Ulman, Venugopal V. Veeravalli
2007	A	`conf`	Utilizing Dynamically Coupled Cores to Form a Resilient Chip Multiprocessor. DSN Christopher LaFrieda, Engin Ipek, José F. Martínez, Rajit Manohar
2006	—	`conf`	A Level-Crossing Flash Asynchronous Analog-to-Digital Converter. ASYNC Filipp Akopyan, Rajit Manohar, Alyssa B. Apsel
2006	—	`conf`	Reconfigurable Asynchronous Logic. CICC Rajit Manohar
2006	—	`conf`	Self-Healing Asynchronous Arrays. ASYNC Song Peng, Rajit Manohar
2006	—	`conf`	Self-Timed Thermally-Aware Circuits. ISVLSI David Fang, Filipp Akopyan, Rajit Manohar
2006	—	`conf`	Yield enhancement of asynchronous logic circuits through 3-dimensional integration technology. ACM Great Lakes Symposium on VLSI Song Peng, Rajit Manohar
2005	Misc	`conf`	A High-Performance Asynchronous FPGA: Test Results. FCCM David Fang, John Teifel, Rajit Manohar
2005	A	`conf`	Automated synthesis for asynchronous FPGAs. FPGA Song Peng, David Fang, John Teifel, Rajit Manohar
2005	—	`conf`	BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor. ASYNC Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar
2005	—	`conf`	Efficient Failure Detection in Pipelined Asynchronous Circuits. DFT Song Peng, Rajit Manohar
2005	C	`conf`	Fault Tolerant Asynchronous Adder through Dynamic Self-reconfiguration. ICCD Song Peng, Rajit Manohar
2005	—	`conf`	Mapping system-on-chip designs from 2-D to 3-D ICs. ISCAS (3) Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, Sandip Tiwari
2004	J	`jnl`	An Asynchronous Dataflow FPGA Architecture. IEEE Trans. Computers John Teifel, Rajit Manohar
2004	A*	`conf`	An ultra low-power processor for sensor networks. ASPLOS Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar
2004	A	`conf`	Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits. DSN Christopher LaFrieda, Rajit Manohar
2004	A	`conf`	Highly pipelined asynchronous FPGAs. FPGA John Teifel, Rajit Manohar
2004	—	`conf`	Non-Uniform Access Asynchronous Register Files. ASYNC David Fang, Rajit Manohar
2004	—	`conf`	Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. ASYNC John Teifel, Rajit Manohar
2003	—	`conf`	A High-Speed Clockless Serial Link Transceiver. ASYNC John Teifel, Rajit Manohar
2003	C	`conf`	An Event-Synchronization Protocol for Parallel Simulation of Large-Scale Wireless Networks. DS-RT Clinton Kelly IV, Rajit Manohar
2003	—	`conf`	Asynchronous DRAM Design and Synthesis. ASYNC Virantha N. Ekanayake, Rajit Manohar
2003	—	`conf`	Power optimal routing in wireless networks. ICC Rajit Manohar, Anna Scaglione
2003	B	`conf`	Programmable Asynchronous Pipeline Arrays. FPL John Teifel, Rajit Manohar
2003	—	`conf`	SNAP: A Sensor-Network Asynchronous Processor. ASYNC Clinton Kelly IV, Virantha N. Ekanayake, Rajit Manohar
2002	—	`conf`	Energy-Efficient Pipelines. ASYNC Rajit Manohar, Clinton Kelly IV, John Teifel, David Fang, David Biermann
2002	A*	`conf`	Scalable formal design methods for asynchronous VLSI. POPL Rajit Manohar
2001	—	`conf`	An Analysis of Reshuffled Handshaking Expansions. ASYNC Rajit Manohar
2001	J	`jnl`	Network on a chip: modeling wireless networks with asynchronous VLSI. IEEE Commun. Mag. Rajit Manohar, Clinton Kelly IV
2001	—	`conf`	Precise Exceptions in Asynchronous Processors. ARVLSI Rajit Manohar, Mika Nyström, Alain J. Martin
2001	—	`conf`	Width-Adaptive Data Word Architectures. ARVLSI Rajit Manohar
1999	J	`jnl`	Joining Specification Statements. Theor. Comput. Sci. K. Rustan M. Leino, Rajit Manohar
1999	—	`conf`	Projection: A Synthesis Technique for Concurrent Systems. ASYNC Rajit Manohar, Tak-Kwan Lee, Alain J. Martin
1999	J	`jnl`	The entropy of traces in parallel computation. IEEE Trans. Inf. Theory Rajit Manohar
1999	—	`—`	The impact of asynchrony on computer architecture. Rajit Manohar
1998	J	`jnl`	Asynchronous Parallel Prefix Computation. IEEE Trans. Computers Rajit Manohar, José A. Tierno
1998	B	`conf`	Slack Elasticity in Concurrent Computing. MPC Rajit Manohar, Alain J. Martin
1997	J	`jnl`	Performance and Portability of an Air Quality Model. Parallel Comput. Donald Dabdub, Rajit Manohar
1997	—	`conf`	The Design of an Asynchronous MIPS R3000 Microprocessor. ARVLSI Alain J. Martin, Andrew Lines, Rajit Manohar, Mika Nyström, Paul I. Pénzes, Robert Southworth, Uri Cummings
1996	—	`conf`	The energy and entropy of VLSI computations. ASYNC José A. Tierno, Rajit Manohar, Alain J. Martin
1995	J	`jnl`	Conditional Composition. Formal Aspects Comput. Rajit Manohar, K. Rustan M. Leino
1995	—	`conf`	Integrating task and data parallelism with the group communication archetype. IPPS K. Mani Chandy, Rajit Manohar, Berna L. Massingill, Daniel I. Meiron