Rajesh Garg

29 papers A* 3A 2B 2C 10Journal 3Unranked 9
YearRankTypeTitle / Venue / Authors
2012 B conf
Patch management automation for enterprise cloud.
NOMS
Hai Huang, Salman Baset, Chunqiang Tang, Ashu Gupta, K. N. Madhu Sudhan, Fazal Feroze, Rajesh Garg, Sumithra Ravichandran
2009 C conf
3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit.
ICCD
Rajesh Garg, Sunil P. Khatri
2009 C conf
A PLL design based on a standing wave resonant oscillator.
ICCD
Vinay Karkala, Kalyana C. Bollapalli, Rajesh Garg, Sunil P. Khatri
2009 C conf
A radiation tolerant Phase Locked Loop design for digital electronics.
ICCD
Rajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal, Sunil P. Khatri
2009 C conf
A robust pulsed flip-flop and its use in enhanced scan design.
ICCD
Rajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri
2009 J jnl
Circuit-Level Design Approaches for Radiation-Hard Digital Electronics.
IEEE Trans. Very Large Scale Integr. Syst.
Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi
2009 — conf
Design and implementation of a sub-threshold BFSK transmitter.
ISQED
Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya
2009 — conf
Efficient analytical determination of the SEU-induced pulse shape.
ASP-DAC
Rajesh Garg, Sunil P. Khatri
2009 J jnl
Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization.
J. Low Power Electron.
Sasidharan Ekambavanan, Rajesh Garg, Sunil P. Khatri, Krishna R. Narayanan
2009 — conf
Low power and high performance sram design using bank-based selective forward body bias.
ACM Great Lakes Symposium on VLSI
Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
2009 C conf
On-chip bidirectional wiring for heavily pipelined systems using network coding.
ICCD
Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
2009 — conf
SEU hardened clock regeneration circuits.
ISQED
Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi
2009 J jnl
Selective Forward Body Bias for High Speed and Low Power SRAMs.
J. Low Power Electron.
Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
2008 A conf
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements.
DATE
Charu Nagpal, Rajesh Garg, Sunil P. Khatri
2008 A conf
A Single-supply True Voltage Level Shifter.
DATE
Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri
2008 A* conf
A fast, analytical estimator for the SEU-induced pulse width in combinational designs.
DAC
Rajesh Garg, Charu Nagpal, Sunil P. Khatri
2008 — conf
A lithography-friendly structured ASIC design approach.
ACM Great Lakes Symposium on VLSI
Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng
2008 C conf
A novel, highly SEU tolerant digital circuit design approach.
ICCD
Rajesh Garg, Sunil P. Khatri
2008 — conf
A robust, fast pulsed flip-flop design.
ACM Great Lakes Symposium on VLSI
Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri
2008 C conf
Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs).
ISCAS
Rajesh Garg, Peng Li, Sunil P. Khatri
2008 — conf
Pipelined network of PLA based circuit design.
ACM Great Lakes Symposium on VLSI
Suganth Paul, Rajesh Garg, Sunil P. Khatri
2007 — conf
A methodology for interconnect dimension determination.
ISPD
Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri
2007 B conf
Low Power UWB Transceiver Design Using Dynamic Voltage Scaling.
WCNC
Rajesh Garg, Chunjie Duan, Jinyun Zhang, Sinan Gezici
2006 A* conf
A PLA based asynchronous micropipelining approach for subthreshold circuit design.
DAC
Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri
2006 A* conf
A design approach for radiation-hard digital electronics.
DAC
Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi
2006 — conf
A design flow to optimize circuit delay by using standard cells and PLAs.
ACM Great Lakes Symposium on VLSI
Rajesh Garg, Mario Sánchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri
2006 C conf
CMOS Comparators for High-Speed and Low-Power Applications.
ICCD
Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri
2006 C conf
Generalized buffering of PTL logic stages using Boolean division.
ISCAS
Rajesh Garg, Sunil P. Khatri
2006 C conf
On the Improvement of Statistical Static Timing Analysis.
ICCD
Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri