Rajesh Galivanche

22 papers A* 1A 6B 1C 1Misc 1Journal 8Unranked 4
YearRankTypeTitle / Venue / Authors
2017 J jnl
New Approaches for Power Binning of High Performance Microprocessors.
IEEE Trans. Computers
Martin Omaña, Marco Padovani, Kreshnik Veliu, Cecilia Metra, Juergen Alt, Rajesh Galivanche
2017 J jnl
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST.
IEEE Trans. Very Large Scale Integr. Syst.
Martin Omaña, Daniele Rossi, Filippo Fuzzi, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche
2016 J jnl
Low-Cost and High-Reduction Approaches for Power Droop during Launch-On-Shift Scan-Based Logic BIST.
IEEE Trans. Computers
Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandrasekharan Tirumurti, Rajesh Galivanche
2014 — conf
Power droop reduction during Launch-On-Shift scan-based logic BIST.
DFT
Martin Omaña, Daniele Rossi, Edda Beniamino, Cecilia Metra, Chandra Tirumurti, Rajesh Galivanche
2013 J jnl
Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder.
J. Electron. Test.
Daniele Rossi, Martin Omaña, G. Garrammone, Cecilia Metra, Abhijit Jas, Rajesh Galivanche
2012 J jnl
Global Signal Vulnerability (GSV) Analysis for Selective State Element Hardening in Modern Microprocessors.
IEEE Trans. Computers
Michail Maniatakos, Chandrasekharan Tirumurti, Rajesh Galivanche, Yiorgos Makris
2011 J jnl
Guest Editors' Introduction: Special Section on Concurrent On-Line Testing and Error/Fault Resilience of Digital Systems.
IEEE Trans. Computers
Cecilia Metra, Rajesh Galivanche
2010 A* conf
Bridging pre-silicon verification and post-silicon validation.
DAC
Amir Nahir, Avi Ziv, Rajesh Galivanche, Alan J. Hu, Miron Abramovici, Albert Camilleri, Bob Bentley, Harry Foster, Valeria Bertacco, Shakti Kapoor
2010 — conf
Low cost and low intrusive approach to test on-line the scheduler of high performance microprocessors.
Conf. Computing Frontiers
Daniele Rossi, Martin Omaña, Gianluca Berghella, Cecilia Metra, Abhijit Jas, Chandra Tirumurti, Rajesh Galivanche
2010 A conf
Path coverage based functional test generation for processor marginality validation.
ITC
Suriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche
2009 J jnl
The Challenges of Nanotechnology and Gigacomplexity.
IEEE Des. Test Comput.
Gadi Singer, Rajesh Galivanche, Srinivas Patil, Mike Tripp
2008 A conf
A low-cost concurrent error detection technique for processor control logic.
DATE
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche
2008 B conf
Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach for High Performance Microprocessor Control Logic.
ETS
Cecilia Metra, Daniele Rossi, Martin Omaña, Abhijit Jas, Rajesh Galivanche
2007 — conf
Test Roles in Diagnosis and Silicon Debug.
ATS
Anis Uzzaman, Fidel Muradali, Takashi Aikyo, Robert C. Aitken, Tom Jackson, Rajesh Galivanche, Takeshi Onodera
2007 A conf
Testing in the year 2020.
DATE
Rajesh Galivanche, Rohit Kapur, Antonio Rubio
2006 Misc conf
Session Abstract.
VTS
Rajesh Galivanche, Bob Gottlieb
2005 A conf
Is the concern for soft-error overblown?
ITC
Rajesh Galivanche
2004 A conf
Trends in manufacturing test methods and their implications.
ITC
Sandip Kundu, T. M. Mak, Rajesh Galivanche
2003 A conf
Circuit and Platform Design Challenges in Technologies beyond 90nm.
DATE
Bill Grundmann, Rajesh Galivanche, Sandip Kundu
2001 J jnl
Test Challenges in Nanometer Technologies.
J. Electron. Test.
Sandip Kundu, Sujit T. Zachariah, Sanjay Sengupta, Rajesh Galivanche
2000 — conf
Test challenges in nanometer technologies.
ETW
Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche
1989 C conf
An automatic test pattern generation program for large ASICs.
ICCD
Dick L. Liu, Rajesh Galivanche, Charlie C. Hsu