Rajesh Amratlal Thakker

22 papers Misc 4Journal 15Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
Remote Sensing Pansharpening with TV-H-1 Decomposition and PSO-Based Adaptive Weighting Method.
Int. J. Image Graph.
Dhara J. Sangani, Rajesh Amratlal Thakker, Sumankumar D. Panchal, Rajesh Gogineni
2023 J jnl
Pan-Sharpening for Spectral Details Preservation Via Convolutional Sparse Coding in Non-Subsampled Shearlet Space.
Int. J. Image Graph.
Dhara J. Sangani, Rajesh Amratlal Thakker, Sumankumar D. Panchal, Rajesh Gogineni
2021 J jnl
Accelerating Parameter Extraction of PSP MOSFET Model on SoC Platform.
J. Circuits Syst. Comput.
Amit Rathod, Rajesh Amratlal Thakker, A. Amalin Prince
2021 J jnl
Parameter extraction of PSP MOSFET model using particle swarm optimisation.
Int. J. Comput. Aided Eng. Technol.
Amit Rathod, Rajesh Amratlal Thakker
2019 J jnl
AGDC: Automatic Garbage Detection and Collection.
CoRR
Siddhant Bansal, Seema Patel, Ishita Shah, Alpesh Patel, Jagruti Makwana, Rajesh Amratlal Thakker
2019 J jnl
Improving the performance of transmission gate and hybrid CMOS Full Adders in chain and tree structure architectures.
Integr.
Manan Mewada, Mazad Zaveri, Rajesh Amratlal Thakker
2019 J jnl
Parameter Space Exploration for Analog Circuit Design Using Enhanced Bee Colony Algorithm.
J. Circuits Syst. Comput.
Subhash J. Patel, Rajesh Amratlal Thakker
2019 Misc conf
Parasitic-Aware Automatic Analog CMOS Circuit Design Environment.
VLSID
Subhash Jagadishchandra Patel, Rajesh Amratlal Thakker
2018 J jnl
A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology.
Integr.
Mitesh Limachia, Rajesh Amratlal Thakker, Nikhil Kothari
2018 J jnl
Hybrid offset compensated latch-type sense amplifier for tri-gated FinFET technology.
Integr.
Mitesh Limachia, Dixit Vyas, Rajesh Amratlal Thakker, Nikhil Kothari
2018 — conf
Parameter Extraction of PSP MOSFET Model Using Particle Swarm Optimization - SoC Approach.
VDAT
Amit Rathod, Rajesh Amratlal Thakker
2018 Misc conf
Parasitic Aware Automatic Analog CMOS Circuit Design Environment Using ABC Algorithm.
VLSID
Subhash J. Patel, Rajesh Amratlal Thakker
2017 Misc conf
Characterization of a Novel 10T Low-Voltage SRAM Cell with High Read and Write Margin for 20nm FinFET Technology.
VLSID
Mitesh Limachia, Pathik Viramgama, Rajesh Amratlal Thakker, Nikhil Kothari
2015 J jnl
Implementation and comparative quantitative assessment of different multispectral image pansharpening approches.
CoRR
Shailesh Panchal, Rajesh Amratlal Thakker
2011 J jnl
A novel architecture for improving slew rate in FinFET-based op-amps and OTAs.
Microelectron. J.
Rajesh Amratlal Thakker, Mayank Srivastava, Ketankumar H. Tailor, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao, Mahesh B. Patil
2010 J jnl
A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rajesh Amratlal Thakker, Chaitanya Sathe, Maryam Shojaei Baghini, Mahesh B. Patil
2010 — conf
Auto-BET-AMS: An automated device and circuit optimization platform to benchmark emerging technologies for performance and variability using an analog and mixed-signal design framework.
ISQED
Angada B. Sachid, Rajesh Amratlal Thakker, Chaitanya Sathe, Maryam Shojaei Baghini, Dinesh Kumar Sharma, V. Ramgopal Rao, Mahesh B. Patil
2009 J jnl
A Novel Table-Based Approach for Design of FinFET Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil
2009 — conf
Automated design and optimization of circuits in emerging technologies.
ASP-DAC
Rajesh Amratlal Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil
2009 J jnl
Automatic Design of Low-Power Low-Voltage Analog Circuits Using Particle Swarm Optimization with Re-Initialization.
J. Low Power Electron.
Rajesh Amratlal Thakker, Maryam Shojaei Baghini, Mahesh B. Patil
2009 Misc conf
Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization.
VLSI Design
Rajesh Amratlal Thakker, Maryam Shojaei Baghini, Mahesh B. Patil
2009 J jnl
Parameter extraction for PSP MOSFET model using hierarchical particle swarm optimization.
Eng. Appl. Artif. Intell.
Rajesh Amratlal Thakker, Mahesh B. Patil, K. G. Anil