Rajendran Panda

62 papers A* 14A 17Misc 1Journal 13Unranked 16

Year	Rank	Type	Title / Venue / Authors
2010	J	`jnl`	Guest Editorial: Special Issue on VLSI Design and Embedded Systems. Int. J. Parallel Program. Preeti Ranjan Panda, Rajendran Panda
2010	J	`jnl`	Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu
2009	—	`conf`	Characterization of sequential cells for constraint sensitivities. ISQED Savithri Sundareswaran, Rajendran Panda, Jacob A. Abraham, Yun Zhang, Amit Mittal
2008	—	`conf`	A timing methodology considering within-die clock skew variations. SoCC Savithri Sundareswaran, Lucie Nechanicka, Rajendran Panda, Sergey Gavrilov, Roman A. Solovyev, Jacob A. Abraham
2008	—	`conf`	Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding. ISQED Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu
2008	—	`conf`	Characterization of Standard Cells for Intra-Cell Mismatch Variations. ISQED Savithri Sundareswaran, Jacob A. Abraham, Alexandre Ardelea, Rajendran Panda
2008	—	`ch.`	Coupling Noise. Handbook of Algorithms for Physical Design Automation Rajendran Panda, Vladimir Zolotov, Murat R. Becer
2007	A	`conf`	A novel technique for incremental analysis of on-chip power distribution networks. ICCAD Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao
2007	A	`conf`	Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding. ICCAD Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu
2007	A*	`conf`	On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise. DAC Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan
2007	J	`jnl`	Stochastic Power Grid Analysis Considering Process Variations CoRR Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang
2006	A*	`conf`	A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming. DAC Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu
2006	J	`jnl`	Impact of stress-induced backflow on full-chip electromigration risk assessment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haldun Haznedar, Martin Gall, Vladimir Zolotov, Pon Sung Ku, Chanhee Oh, Rajendran Panda
2006	J	`jnl`	Optimal placement of power-supply pads and pins. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
2006	A*	`conf`	Stochastic variational analysis of large power grids considering intra-die correlations. DAC Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda
2005	A	`conf`	Pessimism reduction in crosstalk noise aware STA. ICCAD Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Amir Grinshpon, Ilan Algor, Rafi Levy, Chanhee Oh
2005	A	`conf`	Stochastic Power Grid Analysis Considering Process Variations. DATE Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang
2004	—	`conf`	A Methodology for Chip-Level Electromigration Risk Assessment and Product Qualification. ISQED Chanhee Oh, Haldun Haznedar, Martin Gall, Amir Grinshpon, Vladimir Zolotov, Pon Sung Ku, Rajendran Panda
2004	A*	`conf`	A stochastic approach To power grid analysis. DAC Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
2004	J	`jnl`	Crosstalk noise control in an SoC physical design flow. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda
2004	A	`conf`	Delay noise pessimism reduction by logic correlations. ICCAD Alexey Glebov, Sergey Gavrilov, R. Soloviev, Vladimir Zolotov, Murat R. Becer, Chanhee Oh, Rajendran Panda
2004	A	`conf`	False-Noise Analysis for Domino Circuits. DATE Alexey Glebov, Sergey Gavrilov, Vladimir Zolotov, Chanhee Oh, Rajendran Panda, Murat R. Becer
2004	A*	`conf`	Optimal placement of power supply pads and pins. DAC Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
2004	J	`jnl`	Postroute gate sizing for crosstalk noise reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
2003	J	`jnl`	Early probabilistic noise estimation for capacitively coupled interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Murat R. Becer, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
2003	J	`jnl`	Fast on-chip inductance simulation using a precorrected-FFT method. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
2003	J	`jnl`	Impact of Low-Impedance Substrate on Power Supply Integrity. IEEE Des. Test Comput. Rajendran Panda, Savithri Sundareswaran, David T. Blaauw
2003	—	`conf`	Post-Route Gate Sizing for Crosstalk Noise Reduction. ISQED Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
2003	A*	`conf`	Post-route gate sizing for crosstalk noise reduction. DAC Murat R. Becer, David T. Blaauw, Ilan Algor, Rajendran Panda, Chanhee Oh, Vladimir Zolotov, Ibrahim N. Hajj
2003	A	`conf`	SOI Transistor Model for Fast Transient Simulation. ICCAD D. Nadezhin, Sergey Gavrilov, Alexey Glebov, Y. Egorov, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Murat R. Becer, Alexandre Ardelea, A. Patel
2003	—	`conf`	Signal integrity management in an SoC physical design flow. ISPD Murat R. Becer, Ravi Vaidyanathan, Chanhee Oh, Rajendran Panda
2003	—	`conf`	Static Electromigration Analysis for Signal Interconnects. ISQED Chanhee Oh, David T. Blaauw, Murat R. Becer, Vladimir Zolotov, Rajendran Panda, Aurobindo Dasgupta
2003	—	`conf`	Statistical delay computation considering spatial correlations. ASP-DAC Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda
2003	—	`conf`	Table look-up based compact modeling for on-chip interconnect timing and noise analysis. ISCAS (4) Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
2003	A	`conf`	Vectorless Analysis of Supply Noise Induced Delay Variation. ICCAD Sanjay Pant, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
2002	A	`conf`	A precorrected-FFT method for simulating on-chip inductance. ICCAD Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
2002	A	`conf`	Analysis of Noise Avoidance Techniques in DSM Interconnects Using a Complete Crosstalk Noise Model . DATE Murat R. Becer, Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Ibrahim N. Hajj
2002	J	`jnl`	Duet: an accurate leakage estimation and optimization tool for dual-V IEEE Trans. Very Large Scale Integr. Syst. Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Rajendran Panda, David T. Blaauw
2002	—	`conf`	Early probabilistic noise estimation for capacitively coupled interconnects. SLIP Murat R. Becer, David T. Blaauw, Ibrahim N. Hajj, Rajendran Panda
2002	—	`conf`	False-Noise Analysis Using Resolution Method. ISQED Alexey Glebov, Sergey Gavrilov, David T. Blaauw, Vladimir Zolotov, Rajendran Panda, Chanhee Oh
2002	J	`jnl`	Hierarchical analysis of power distribution networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw
2002	—	`conf`	Noise Injection and Propagation in High Performance Designs. ISQED Vladimir Zolotov, David T. Blaauw, Rajendran Panda, Chanhee Oh
2002	A	`conf`	Noise propagation and failure criteria for VLSI designs. ICCAD Vladimir Zolotov, David T. Blaauw, Supamas Sirichotiyakul, Murat R. Becer, Chanhee Oh, Rajendran Panda, Amir Grinshpon, Rafi Levy
2002	—	`conf`	Pre-route Noise Estimation in Deep Submicron Integrated Circuits. ISQED Murat R. Becer, Rajendran Panda, David T. Blaauw, Ibrahim N. Hajj
2002	—	`conf`	Worst case clock skew under power supply variations. Timing Issues in the Specification and Synthesis of Digital Systems Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal
2001	A	`conf`	On the interaction of power distribution network with substrate. ISLPED Rajendran Panda, Savithri Sundareswaran, David T. Blaauw
2000	A*	`conf`	Current signature compression for IR-drop analysis. DAC Rajat Chaudhry, David T. Blaauw, Rajendran Panda, Tim Edwards
2000	Misc	`conf`	Design and Analysis of Power Distribution Networks with Accurate RLC Models. VLSI Design Rajat Chaudhry, Rajendran Panda, Tim Edwards, David T. Blaauw
2000	A*	`conf`	Hierarchical analysis of power distribution networks. DAC Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw
2000	A	`conf`	Model and analysis for combined package and on-chip power grid simulation. ISLPED Rajendran Panda, David T. Blaauw, Rajat Chaudhry, Vladimir Zolotov, Brian Young, Ravi Ramaraju
2000	A*	`conf`	On-chip inductance modeling and analysis. DAC Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David T. Blaauw
2000	—	`conf`	On-chip inductance modeling. ACM Great Lakes Symposium on VLSI David T. Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang
2000	A*	`conf`	Removing user specified false paths from timing graphs. DAC David T. Blaauw, Rajendran Panda, Abhijit Das
2000	A	`conf`	Slope Propagation in Static Timing Analysis. ICCAD David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Chanhee Oh, Rajendran Panda
1999	A*	`conf`	Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing. DAC Supamas Sirichotiyakul, Tim Edwards, Chanhee Oh, Jingyan Zuo, Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw
1998	A	`conf`	CMOS Combinational Circuit Sizing by Stage-wise Tapering. DATE Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija
1998	A*	`conf`	Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. DAC Abhijit Dharchoudhury, Rajendran Panda, David T. Blaauw, Ravi Vaidyanathan, Bogdan Tutuianu, David Bearden
1998	A	`conf`	Emerging power management tools for processor design. ISLPED David T. Blaauw, Abhijit Dharchoudhury, Rajendran Panda, Supamas Sirichotiyakul, Chanhee Oh, Tim Edwards
1998	A*	`conf`	Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. DAC Rajendran Panda, Abhijit Dharchoudhury, Tim Edwards, Joe Norton, David T. Blaauw
1998	J	`jnl`	Post-Mapping Transformations for Low-Power Synthesis. VLSI Design Rajendran Panda, Farid N. Najm
1997	A	`conf`	Library-less synthesis for static CMOS combinational logic circuits. ICCAD Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw
1997	A*	`conf`	Technology-Dependent Transformations for Low-Power Synthesis. DAC Rajendran Panda, Farid N. Najm