Rajendra Kumar Nagaria

26 papers Misc 1Journal 21Unranked 4
YearRankTypeTitle / Venue / Authors
2025 J jnl
A low power noise tolerant wide fan-in OR logic domino gate.
Integr.
Ankur Kumar, Naman Garg, Rajendra Kumar Nagaria
2025 J jnl
Design Techniques for High-Speed and Low Power SAR ADC: A Review.
J. Circuits Syst. Comput.
Vikas Tiwari, Rajendra Kumar Nagaria
2025 J jnl
Energy efficient anchor zone based routing protocol for IoT networks.
Comput. Electr. Eng.
Naveen Kumar Gupta, Garima, Rama Shankar Yadav, Rajendra Kumar Nagaria
2025 Misc conf
Self Organized Anchor Group based Routing Protocol for IoT Initial Setup.
COMSNETS
Naveen Kumar Gupta, Apeksha Aggarwal, Rama Shankar Yadav, Rajendra Kumar Nagaria
2023 J jnl
Anchor-based void detouring routing protocol in three dimensional IoT networks.
Comput. Networks
Naveen Kumar Gupta, Rama Shankar Yadav, Rajendra Kumar Nagaria, Deepak Gupta, Achyut Mani Tripathi, Om Jee Pandey
2023 J jnl
Reduction of variation and leakage in wide fan-in OR Logic domino gate.
Integr.
Ankur Kumar, Rajendra Kumar Nagaria
2022 J jnl
A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-In OR Logic.
J. Circuits Syst. Comput.
Ankur Kumar, Rajendra Kumar Nagaria
2021 J jnl
An Angular 3D Path Selection Protocol in Wireless Sensor Networks.
Open Comput. Sci.
Naveen Kumar Gupta, Rama Shankar Yadav, Rajendra Kumar Nagaria, Deepak Gupta
2021 J jnl
Design and Performance of High-Speed Energy-Efficient CMOS Double Tail Dynamic Latch Comparator Using GACOBA Load Suitable for Low Voltage Applications.
J. Circuits Syst. Comput.
Vikrant Varshney, Avaneesh K. Dubey, Rajendra Kumar Nagaria
2020 J jnl
3D geographical routing protocols in wireless ad hoc and sensor networks: an overview.
Wirel. Networks
Naveen Kumar Gupta, Rama Shankar Yadav, Rajendra Kumar Nagaria
2020 J jnl
A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load.
Integr.
Pratosh Kumar Pal, Rajendra Kumar Nagaria
2020 — conf
Anchor Based Geographical Routing in WSN.
ICSCA
Naveen Kumar Gupta, Rama Shankar Yadav, Rajendra Kumar Nagaria
2019 J jnl
A Low-Power, Sub-1-V All-MOSFET Subthreshold Voltage Reference Using Body Biasing.
J. Circuits Syst. Comput.
Pratosh Kumar Pal, Rajendra Kumar Nagaria
2019 J jnl
Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect.
J. Circuits Syst. Comput.
Avaneesh K. Dubey, Rajendra Kumar Nagaria
2019 — conf
Energy Efficient Angle based Route Selection in 3D Wireless Sensor Networks.
SICE
Naveen Kumar Gupta, Rama Shankar Yadav, Rajendra Kumar Nagaria
2018 J jnl
A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits.
Integr.
Ankur Kumar, Rajendra Kumar Nagaria
2018 J jnl
Energy efficient neoteric design of a 3-input Majority Gate with its implementation and physical proof in Quantum dot Cellular Automata.
Nano Commun. Networks
Sankit R. Kassa, Rajendra Kumar Nagaria, R. Karthik
2018 J jnl
Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique.
J. Circuits Syst. Comput.
Avaneesh K. Dubey, Rajendra Kumar Nagaria
2018 J jnl
Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load.
Microelectron. J.
Avaneesh K. Dubey, Rajendra Kumar Nagaria
2017 J jnl
A Novel Design for 4-Bit Code Converters in Quantum Dot Cellular Automata.
J. Low Power Electron.
Sankit R. Kassa, Rajendra Kumar Nagaria
2016 J jnl
An Innovative Low Power Full Adder Design in Nano Technology Based Quantum Dot Cellular Automata.
J. Low Power Electron.
Sankit R. Kassa, Rajendra Kumar Nagaria
2015 — conf
A Review on Robust Low Power System Level Digital Circuit Design Approaches in Nano-CMOS Technologies.
ICCCT
Sankit R. Kassa, Rajendra Kumar Nagaria
2013 J jnl
Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic.
VLSI Design
Shipra Upadhyay, Rajendra Kumar Nagaria, Ram Awadh Mishra
2012 J jnl
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design.
VLSI Design
Subodh Wairya, Rajendra Kumar Nagaria, Sudarshan Tiwari
2010 J jnl
On the New Design of sinusoid voltage Controlled oscillators Using Multiplier in CFA-Based Double Integrator Loop.
J. Circuits Syst. Comput.
Rajendra Kumar Nagaria, Rakesh Kumar Singh, Subodh Wairya
2009 — conf
PAPR Reduction for OFDM Scheme by New Partial Transmit Sequence Technique in Wireless Communication Systems.
CICSyN
Pankaj Kumar Sharma, Rajendra Kumar Nagaria, T. N. Sharma