Rajendra Bishnoi

97 papers A* 2A 27B 5C 5Misc 3Journal 31Unranked 23

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	PHANTOM: Power Hammering Attack and Countermeasure on Multi-Tenant ReRAM Compute-in-Memory Accelerators. IEEE Trans. Inf. Forensics Secur. Ashish Reddy Bommana, Rajendra Bishnoi, Naghmeh Karimi, Farshad Firouzi, Krishnendu Chakrabarty
2026	—	`conf`	SABCIM: Self-Adaptive Biasing Scheme for Accurate and Efficient Analog Compute-in-Memory. ASP-DAC Yashvardhan Biyani, Abhairaj Singh, Rajendra Bishnoi, Said Hamdioui
2025	A	`conf`	Adaptive Multi-Threshold Encoding for Energy-Efficient ECG Classification Architecture Using Spiking Neural Network. DATE Sumit Diware, Yingzhou Dong, Mohammad Amin Yaldagard, Said Hamdioui, Rajendra Bishnoi
2025	A	`conf`	C3CIM: Constant Column Current Memristor-Based Computation-in-Memory Micro-Architecture. DATE Yashvardhan Biyani, Rajendra Bishnoi, Theofilos Spyrou, Said Hamdioui
2025	A	`conf`	Continuous On-Chip Learning in Neural Networks using SOT-MRAM based CIM Architectures. ICCAD Anubha Sehgal, Sandeep Soni, Sumit Diware, Alok Kumar Shukla, Sourajeet Roy, Rajendra Bishnoi
2025	A	`conf`	Energy-Efficient Multi-Operand XOR Logic-Based CIM Accelerator using RRAM technology. ICCAD Abhairaj Singh, Konstantinos Stavrakakis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui
2025	A*	`conf`	Enhancing Parallelism and Energy-Efficiency in SOT-MRAM based CIM Architecture for On-Chip Learning. DAC Anubha Sehgal, Alok Kumar Shukla, Sumit Diware, Sandeep Soni, Seema Dhull, Sonal Shreya, Sourajeet Roy, Rajendra Bishnoi
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025	B	`conf`	In-Field Monitoring and Preventing Read Disturb Faults in RRAMs. ETS Hanzhi Xun, Moritz Fieback, Sicong Yuan, Changhao Wang, Erbing Hua, Hassen Aziza, Leticia Bolzani Poehls, Riccardo Cantoro, Rajendra Bishnoi, Mottaqiallah Taouil, Said Hamdioui
2025	A	`conf`	Multi-Partner Project: A Deep Learning Platform Targeting Embedded Hardware for Edge-AI Applications (NEUROKIT2E). DATE Rajendra Bishnoi, Mohammad Amin Yaldagard, Said Hamdioui, Kanishkan Vadivel, Manolis Sifalakis, Nicolas Daniel Rodriguez, Pedro Julián, Lothar Ratschbacher, Maen Mallah, Yogesh Ramesh Patil, Rashid Ali, Fabian Chersi
2024	—	`conf`	A Lightweight Architecture for Real-Time Neuronal-Spike Classification. CF Muhammad Ali Siddiqi, David Vrijenhoek, Lennart P. L. Landsmeer, Job van der Kleij, Anteneh Gebregiorgis, Vincenzo Romano, Rajendra Bishnoi, Said Hamdioui, Christos Strydis
2024	—	`conf`	Dynamic Detection and Mitigation of Read-disturb for Accurate Memristor-based Neural Networks. AICAS Sumit Diware, Mohammad Amin Yaldagard, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
2024	A*	`conf`	Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning. DAC Lucas Huijbregts, Hsiao-Hsuan Liu, Paul Detterer, Said Hamdioui, Amirreza Yousefzadeh, Rajendra Bishnoi
2024	J	`jnl`	Energy-efficient SNN Architecture using 3nm FinFET Multiport SRAM-based CIM with Online Learning. CoRR Lucas Huijbregts, Hsiao-Hsuan Liu, Paul Detterer, Said Hamdioui, Amirreza Yousefzadeh, Rajendra Bishnoi
2024	A	`conf`	Hardware-Aware Quantization for Accurate Memristor-Based Neural Networks. ICCAD Sumit Diware, Mohammad Amin Yaldagard, Rajendra Bishnoi
2024	J	`jnl`	Memristor-Based Lightweight Encryption. CoRR Muhammad Ali Siddiqi, Jan Andrés Galvan Hernández, Anteneh Gebregiorgis, Rajendra Bishnoi, Christos Strydis, Said Hamdioui, Mottaqiallah Taouil
2024	—	`conf`	Real-Time Supervised Spiking Neural Network for Cerebellar Purkinje Cells Spike Detection and Classification. ICONS Alireza Raisiardali, Muhammad Ali Siddiqi, Christos Strydis, Said Hamdioui, Dante Gabriel Muratore, Rajendra Bishnoi
2024	J	`jnl`	Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks. IEEE Access Sumit Diware, Koteswararao Chilakala, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
2023	—	`conf`	A 115.1 TOPS/W, 12.1 TOPS/mm AICAS Abhairaj Singh, Rajendra Bishnoi, Ali Kaichouhi, Sumit Diware, Rajiv V. Joshi, Said Hamdioui
2023	J	`jnl`	A Lightweight Architecture for Real-Time Neuronal-Spike Classification. CoRR Muhammad Ali Siddiqi, David Vrijenhoek, Lennart P. L. Landsmeer, Job van der Kleij, Anteneh Gebregiorgis, Vincenzo Romano, Rajendra Bishnoi, Said Hamdioui, Christos Strydis
2023	J	`jnl`	Accurate and Energy-Efficient Bit-Slicing for RRAM-Based Neural Networks. IEEE Trans. Emerg. Top. Comput. Intell. Sumit Diware, Abhairaj Singh, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
2023	B	`conf`	Dependability of Future Edge-AI Processors: Pandora's Box. ETS Manil Dev Gomony, Anteneh Gebregiorgis, Moritz Fieback, Marc Geilen, Sander Stuijk, Jan Richter-Brockmann, Rajendra Bishnoi, Sven Argo, Lara Arche Andradas, Tim Güneysu, Mottaqiallah Taouil, Henk Corporaal, Said Hamdioui
2023	—	`conf`	Energy-efficient Computation-In-Memory Architecture using Emerging Technologies. ICM Rajendra Bishnoi, Sumit Diware, Anteneh Gebregiorgis, Simon Thomann, Sara Mannaa, Bastien Deveautour, Cédric Marchand, Alberto Bosio, Damien Deleruyelle, Ian O'Connor, Hussam Amrouch, Said Hamdioui
2023	—	`conf`	Mapping-aware Biased Training for Accurate Memristor-based Neural Networks. AICAS Sumit Diware, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
2023	C	`conf`	Memristor-Based Lightweight Encryption. DSD Muhammad Ali Siddiqi, Jan Andrés Galvan Hernández, Anteneh Gebregiorgis, Rajendra Bishnoi, Christos Strydis, Said Hamdioui, Mottaqiallah Taouil
2023	C	`conf`	On the Reliability of RRAM-Based Neural Networks. VLSI-SoC Hassen Aziza, Cristian Zambelli, Said Hamdioui, Sumit Diware, Rajendra Bishnoi, Anteneh Gebregiorgis
2023	A	`conf`	PetaOps/W edge-AI $\mu$ Processors: Myth or reality? DATE Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal
2023	—	`conf`	Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture. AICAS Mohammad Amin Yaldagard, Sumit Diware, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
2023	J	`jnl`	Severity-Based Hierarchical ECG Classification Using Neural Networks. IEEE Trans. Biomed. Circuits Syst. Sumit Diware, Sudeshna Dash, Anteneh Gebregiorgis, Rajiv V. Joshi, Christos Strydis, Said Hamdioui, Rajendra Bishnoi
2022	J	`jnl`	A Survey on Memory-centric Computer Architectures. ACM J. Emerg. Technol. Comput. Syst. Anteneh Gebregiorgis, Hoang Anh Du Nguyen, Jintao Yu, Rajendra Bishnoi, Mottaqiallah Taouil, Francky Catthoor, Said Hamdioui
2022	J	`jnl`	A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs. ACM J. Emerg. Technol. Comput. Syst. Mahta Mayahinia, Abhairaj Singh, Christopher Bengel, Stefan Wiefels, Muath Abu Lebdeh, Stephan Menzel, Dirk J. Wouters, Anteneh Gebregiorgis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui
2022	A	`conf`	Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT. ITC Abhairaj Singh, Moritz Fieback, Rajendra Bishnoi, Filip Bradaric, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui
2022	—	`conf`	CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out. AICAS Abhairaj Singh, Mahdi Zahedi, Taha Shahroodi, Mohit Gupta, Anteneh Gebregiorgis, Manu Komalan, Rajiv V. Joshi, Francky Catthoor, Rajendra Bishnoi, Said Hamdioui
2022	J	`jnl`	CONVOLVE: Smart and seamless design of smart edge processors. CoRR Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Frank K. Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, S. Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal
2022	C	`conf`	Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs. VLSI-SoC Anteneh Gebregiorgis, Abhairaj Singh, Sumit Diware, Rajendra Bishnoi, Said Hamdioui
2022	J	`jnl`	Defects, Fault Modeling, and Test Development Framework for RRAMs. ACM J. Emerg. Technol. Comput. Syst. Moritz Fieback, Guilherme Cardoso Medeiros, Lizhou Wu, Hassen Aziza, Rajendra Bishnoi, Mottaqiallah Taouil, Said Hamdioui
2022	A	`conf`	Referencing-in-Array Scheme for RRAM-based CIM Architecture. DATE Abhairaj Singh, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui
2022	J	`jnl`	Reliability aspects of binary vector-matrix-multiplications using ReRAM devices. Neuromorph. Comput. Eng. Christopher Bengel, Johannes Mohr, Stefan Wiefels, Abhairaj Singh, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Rainer Waser, Dirk J. Wouters, Stephan Menzel
2021	J	`jnl`	A Survey of Test and Reliability Solutions for Magnetic Random Access Memories. Proc. IEEE Patrick Girard, Yuanqing Cheng, Arnaud Virazel, Wei Zhao, Rajendra Bishnoi, Mehdi B. Tahoori
2021	C	`conf`	Low-Power Memristor-Based Computing for Edge-AI Applications. ISCAS Abhairaj Singh, Sumit Diware, Anteneh Gebregiorgis, Rajendra Bishnoi, Francky Catthoor, Rajiv V. Joshi, Said Hamdioui
2021	J	`jnl`	SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures. IEEE Trans. Circuits Syst. I Regul. Pap. Abhairaj Singh, Muath Abu Lebdeh, Anteneh Gebregiorgis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui
2021	—	`conf`	Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture. AICAS Sumit Diware, Anteneh Gebregiorgis, Rajiv V. Joshi, Said Hamdioui, Rajendra Bishnoi
2020	J	`jnl`	A Compact Low-Voltage True Random Number Generator Based on Inkjet Printing Technology. IEEE Trans. Very Large Scale Integr. Syst. Ahmet Turan Erozan, Guan Ying Wang, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori
2020	J	`jnl`	A Novel Printed-Lookup-Table-Based Programmable Printed Digital Circuit. IEEE Trans. Very Large Scale Integr. Syst. Ahmet Turan Erozan, Dennis D. Weller, Farhan Rasheed, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori
2020	A	`conf`	A Universal Spintronic Technology based on Multifunctional Standardized Stack. DATE Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Lionel Torres, Sophiane Senni, Guillaume Patrigeon, Pascal Benoit, Gregory di Pendina, Guillaume Prenat
2020	J	`jnl`	Approximate Spintronic Memories. ACM J. Emerg. Technol. Comput. Syst. Nour Sayed, Rajendra Bishnoi, Mehdi B. Tahoori
2020	J	`jnl`	Crossover-aware Placement and Routing for Inkjet Printed Circuits. ACM J. Emerg. Technol. Comput. Syst. Farhan Rasheed, Michael Hefenbrock, Rajendra Bishnoi, Michael Beigl, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori
2020	A	`conf`	Dynamic Faults based Hardware Trojan Design in STT-MRAM. DATE Sarath Mohanachandran Nair, Rajendra Bishnoi, Arunkumar Vijayan, Mehdi Baradaran Tahoori
2020	Misc	`conf`	Mitigating Read Failures in STT-MRAM. VTS Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2020	—	`conf`	Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects. IRPS Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi B. Tahoori, Houman Zahedmanesh, Kristof Croes, Kevin Garello, Gouri Sankar Kar, Francky Catthoor
2020	J	`jnl`	Secure STT-MRAM Bit-Cell Design Resilient to Differential Power Analysis Attacks. IEEE Trans. Very Large Scale Integr. Syst. Samir Ben Dodo, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2020	Misc	`conf`	Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis. VTS Rajendra Bishnoi, Lizhou Wu, Moritz Fieback, Christopher Münch, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori, Ying Wang, Huawei Li, Said Hamdioui
2020	B	`conf`	Testing Scouting Logic-Based Computation-in-Memory Architectures. ETS Moritz Fieback, Surya Nagarajan, Rajendra Bishnoi, Mehdi B. Tahoori, Mottaqiallah Taouil, Said Hamdioui
2020	—	`conf`	Tolerating Retention Failures in Neuromorphic Fabric based on Emerging Resistive Memories. ASP-DAC Christopher Münch, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2019	J	`jnl`	A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM. IEEE Trans. Very Large Scale Integr. Syst. Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2019	J	`jnl`	A Comprehensive Reliability Analysis Framework for NTC Caches: A System to Device Approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Anteneh Gebregiorgis, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2019	J	`jnl`	A Spintronics Memory PUF for Resilience Against Cloning Counterfeit. IEEE Trans. Very Large Scale Integr. Syst. Samir Ben Dodo, Rajendra Bishnoi, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori
2019	J	`jnl`	Compiler-Assisted and Profiling-Based Analysis for Fast and Efficient STT-MRAM On-Chip Cache Design. ACM Trans. Design Autom. Electr. Syst. Nour Sayed, Longfei Mao, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2019	J	`jnl`	Fast and Reliable STT-MRAM Using Nonuniform and Adaptive Error Detecting and Correcting Scheme. IEEE Trans. Very Large Scale Integr. Syst. Nour Sayed, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2019	A	`conf`	Inkjet-Printed True Random Number Generator based on Additive Resistor Tuning. DATE Ahmet Turan Erozan, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori
2019	A	`conf`	Predictive Modeling and Design Automation of Inorganic Printed Electronics. DATE Farhan Rasheed, Michael Hefenbrock, Rajendra Bishnoi, Michael Beigl, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori
2019	—	`conf`	Reliable in-memory neuromorphic computing using spintronics. ASP-DAC Christopher Münch, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2019	—	`conf`	Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects. IRPS Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Houman Zahedmanesh, Kristof Croes, Kevin Garello, Gouri Sankar Kar, Francky Catthoor
2019	C	`conf`	Variation-aware Fault Modeling and Test Generation for STT-MRAM. IOLTS Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Hayk T. Grigoryan, Grigor Tshagharyan
2018	A	`conf`	A cross-layer adaptive approach for performance and power optimization in STT-MRAM. DATE Nour Sayed, Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori
2018	A	`conf`	Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM. ITC Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Hayk T. Grigoryan, Gurgen Harutyunyan, Yervant Zorian
2018	—	`conf`	Design and evaluation of physical unclonable function for inorganic printed electronics. ISQED Ahmet Turan Erozan, Mohammad Saber Golanbari, Rajendra Bishnoi, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori
2018	J	`jnl`	Inkjet-Printed EGFET-Based Physical Unclonable Function - Design, Evaluation, and Fabrication. IEEE Trans. Very Large Scale Integr. Syst. Ahmet Turan Erozan, Gabriel Cadilha Marques, Mohammad Saber Golanbari, Rajendra Bishnoi, Simone Dehm, Jasmin Aghassi-Hagmann, Mehdi Baradaran Tahoori
2018	A	`conf`	Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications. ITC Grigor Tshagharyan, Gurgen Harutyunyan, Yervant Zorian, Anteneh Gebregiorgis, Mohammad Saber Golanbari, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2018	A	`conf`	Multi-bit non-volatile spintronic flip-flop. DATE Christopher Münch, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2018	A	`conf`	Parametric failure modeling and yield analysis for STT-MRAM. DATE Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2018	—	`conf`	Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM. ASP-DAC Nour Sayed, Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2018	—	`conf`	Reliable memory PUF design for low-power applications. ISQED Mohammad Saber Golanbari, Saman Kiamehr, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2018	A	`conf`	Spintronic normally-off heterogeneous system-on-chip design. DATE Anteneh Gebregiorgis, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2018	A	`conf`	Using multifunctional standardized stack as universal spintronic technology for IoT. DATE Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Abdoulaye Gamatié, Pascal Nouet, Frederic Ouattara, Gilles Sassatelli, Kotb Jabeur, Pierre Vanhauwaert, A. Atitoaie, I. Firastrau, Gregory di Pendina, Guillaume Prenat
2018	J	`jnl`	VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Fazal Hameed, Mehdi Baradaran Tahoori
2017	—	`conf`	Architecting SOT-RAM Based GPU Register File. ISVLSI Sparsh Mittal, Rajendra Bishnoi, Fabian Oboril, Haonan Wang, Mehdi Baradaran Tahoori, Adwait Jog, Jeffrey S. Vetter
2017	J	`jnl`	Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori
2017	B	`conf`	Exploiting STT-MRAM for approximate computing. ETS Nour Sayed, Fabian Oboril, Azadeh Shirvanian, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2017	—	`conf`	GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack. ISVLSI Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Pascal Nouet, Rui Ma, Martin Kreißig, Frank Ellinger, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Guillaume Prenat
2017	Misc	`conf`	Leveraging Systematic Unidirectional Error-Detecting Codes for fast STT-MRAM cache. VTS Nour Sayed, Fabian Oboril, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2017	A	`conf`	Opportunistic write for fast and reliable STT-MRAM. DATE Nour Sayed, Mojtaba Ebrahimi, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2017	—	`—`	Reliable Low-Power High Performance Spintronic Memories Rajendra Bishnoi
2017	A	`conf`	VAET-STT: A variation aware estimator tool for STT-MRAM based memories. DATE Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Mehdi Baradaran Tahoori
2016	A	`conf`	A cross-layer analysis of Soft Error, aging and process variation in Near Threshold Computing. DATE Anteneh Gebregiorgis, Saman Kiamehr, Fabian Oboril, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2016	A	`conf`	Fault Tolerant Non-Volatile spintronic flip-flop. DATE Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori
2016	J	`jnl`	Layout-Based Modeling and Mitigation of Multiple Event Transients. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mojtaba Ebrahimi, Hossein Asadi, Rajendra Bishnoi, Mehdi Baradaran Tahoori
2016	—	`conf`	Low-Power Multi-Port Memory Architecture based on Spin Orbit Torque Magnetic Devices. ACM Great Lakes Symposium on VLSI Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori
2016	—	`conf`	Non-Volatile Non-Shadow flip-flop using Spin Orbit Torque for efficient normally-off computing. ASP-DAC Rajendra Bishnoi, Fabian Oboril, Mehdi Baradaran Tahoori
2016	A	`conf`	Normally-OFF STT-MRAM Cache with Zero-Byte Compression for Energy Efficient Last-Level Caches. ISLPED Fabian Oboril, Fazal Hameed, Rajendra Bishnoi, Ali Ahari, Helia Naeimi, Mehdi Baradaran Tahoori
2016	J	`jnl`	Self-Timed Read and Write Operations in STT-MRAM. IEEE Trans. Very Large Scale Integr. Syst. Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori
2016	J	`jnl`	Ultra-Fast and High-Reliability SOT-MRAM: From Cache Replacement to Normally-Off Computing. IEEE Trans. Multi Scale Comput. Syst. Guillaume Prenat, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Fabian Oboril, Rajendra Bishnoi, Mojtaba Ebrahimi, Nathalie Lamard, Olivier Boulle, Kevin Garello, Juergen Langer, Berthold Ocker, Marie Claire Cyrille, Pietro Gambardella, Mehdi Baradaran Tahoori, Gilles Gaudin
2015	J	`jnl`	Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fabian Oboril, Rajendra Bishnoi, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori
2014	—	`conf`	Architectural aspects in design and analysis of SOT-based memories. ASP-DAC Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori
2014	A	`conf`	Asynchronous Asymmetrical Write Termination (AAWT) for a low power STT-MRAM. DATE Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori
2014	—	`conf`	Avoiding unnecessary write operations in STT-MRAM for low power implementation. ISQED Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori
2014	A	`conf`	Read disturb fault detection in STT-MRAM. ITC Rajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori