Rajeev Murgai - RankMe

47 papers A* 5A 17C 4Misc 8Journal 4Unranked 9

Year	Rank	Type	Title / Venue / Authors
2018	A	`conf`	SAT-based redundancy removal. DATE Krishanu Debnath, Rajeev Murgai, Mayank Jain, Janet Olson
2015	J	`jnl`	Technology-Dependent Logic Optimization. Proc. IEEE Rajeev Murgai
2009	J	`jnl`	Efficient Power Network Analysis Considering Multidomain Clock Gating. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wanping Zhang, Wenjian Yu, Xiang Hu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng
2008	A	`conf`	Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network. DATE Wanping Zhang, Yi Zhu, Wenjian Yu, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Nuriyoki Ito, Chung-Kuan Cheng
2007	Misc	`conf`	An Efficient Uncertainty- and Skew-aware Methodology for Clock Tree Synthesis and Analysis. VLSI Design Vineet Wason, Rajeev Murgai, William W. Walker
2007	—	`conf`	Design and Analysis of "Tree+Local Meshes" Clock Architecture. ISQED Gustavo R. Wilke, Rajeev Murgai
2007	C	`conf`	Fast power network analysis with multiple clock domains. ICCD Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng
2006	Misc	`conf`	Accurate Substrate Noise Analysis Based on Library Module Characterization. VLSI Design Subodh M. Reddy, Rajeev Murgai
2006	A	`conf`	Analyzing timing uncertainty in mesh-based clock architectures. DATE Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai
2006	—	`conf`	Clock Distribution Architectures: A Comparative Study. ISQED Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai
2005	A	`conf`	A sliding window scheme for accurate clock mesh analysis. ICCAD Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai
2005	J	`jnl`	ADAMIN: automated, accurate macromodeling of digital aggressors for power and ground supply noise prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury
2005	Misc	`conf`	Improved Layout-Driven Area-Constrained Timing Optimization by Net Buffering. VLSI Design Rajeev Murgai
2004	A	`conf`	Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction. DATE Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury
2004	—	`conf`	Macromodeling of digital libraries for substrate noise analysis. ISCAS (5) Zhe Wang, Rajeev Murgai, Jaijeet S. Roychowdhury
2004	Misc	`conf`	Net Buffering in the Presence of Multiple Timing Views. VLSI Design Rajeev Murgai
2004	A	`conf`	Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis. DATE Rajeev Murgai, Subodh M. Reddy, Takashi Miyoshi, Takeshi Horie, Mehdi Baradaran Tahoori
2004	C	`conf`	XTalkDelay: A Crosstalk-Aware Timing Analysis Tool for Chip-Level Designs. ICCD Yinghua Li, Rajeev Murgai, Takashi Miyoshi, Ashwini Verma
2003	J	`jnl`	On the problem of gate assignment under different rise and fall delays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Arlindo L. Oliveira, Rajeev Murgai
2003	—	`conf`	PDL: A New Physical Synthesis Methodology. ISQED Toshiyuki Shibuya, Rajeev Murgai, Tadashi Konno, Kazuhiro Emi, Kaoru Kawamura
2002	—	`conf`	Layout-Driven Timing Optimization by Generalized De Morgan Transform. ASP-DAC/VLSI Design Supratik Chakraborty, Rajeev Murgai
2002	—	`conf`	Net Buffering in the Presence of Multiple Timing Views. IWLS Rajeev Murgai
2001	Misc	`conf`	Complexity Of Minimum-Delay Gate Resizing. VLSI Design Supratik Chakraborty, Rajeev Murgai
2001	—	`conf`	Efficient global fanout optimization algorithms. ASP-DAC Rajeev Murgai
2000	A	`conf`	An Exact Gate Assignment Algorithm for Tree Circuits Under Rise and Fall Delays. ICCAD Arlindo L. Oliveira, Rajeev Murgai
2000	Misc	`conf`	Delay-Constrained Area Recovery Via Layout-Driven Buffer Optimization. VLSI Design Rajeev Murgai
2000	A	`conf`	Layout-Driven Area-Constrained Timing Optimization by Net Buffering. ICCAD Rajeev Murgai
1999	Misc	`conf`	Efficient Scheduling Techniques for ROBDD Construction. VLSI Design Rajeev Murgai, Jawahar Jain, Masahiro Fujita
1999	A	`conf`	On Reducing Transitions Through Data Modifications. DATE Rajeev Murgai, Masahiro Fujita
1999	A	`conf`	On the global fanout optimization problem. ICCAD Rajeev Murgai
1999	A	`conf`	Performance optimization under rise and fall parameters. ICCAD Rajeev Murgai
1999	—	`conf`	Speeding Up Look-up-Table Driven Logic Simulation. VLSI Rajeev Murgai, Fumiyasu Hirose, Masahiro Fujita
1998	A*	`conf`	Using Complementation and Resequencing to Minimize Transitions. DAC Rajeev Murgai, Masahiro Fujita, Arlindo L. Oliveira
1997	Misc	`conf`	Some Recent Advances in Software and Hardware Logic Simulation. VLSI Design Rajeev Murgai, Masahiro Fujita
1997	A	`conf`	Speeding up technology-independent timing optimization by network partitioning. ICCAD Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita
1995	—	`conf`	Decomposition of logic functions for minimum transition activity. ED&TC Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1995	C	`conf`	Logic synthesis for a single large look-up table. ICCD Rajeev Murgai, Masahiro Fujita, Fumiyasu Hirose
1994	A*	`conf`	Optimum Functional Decomposition Using Encoding. DAC Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	A	`conf`	Cube-packing and two-level minimization. ICCAD Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	A*	`conf`	Sequential Synthesis for Table Look Up Programmable Gate Arrays. DAC Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	C	`conf`	Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. ICCD Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	A*	`conf`	An Improved Synthesis Algorithm for Multiplexor-Based PGA's. DAC Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	A	`conf`	Improved Logic Synthesis Algorithms for Table Look Up Architectures. ICCAD Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	A	`conf`	On Clustering for Minimum Delay/Area. ICCAD Rajeev Murgai, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	A	`conf`	Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. ICCAD Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1990	A*	`conf`	Logic Synthesis for Programmable Gate Arrays. DAC Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1989	A	`conf`	SLIP: a software environment for system level interactive partitioning. ICCAD Mark Beardslee, Chuck Kring, Rajeev Murgai, Hamid Savoj, Robert K. Brayton, A. Richard Newton