Rajeev K. Chauhan

12 papers Journal 7Unranked 5
YearRankTypeTitle / Venue / Authors
2024 J jnl
Reconfigurable Image Confusion Scheme Using Large Period Pseudorandom Bit Generator Based on Coupled-Variable Input LCG and Clock Divider.
J. Circuits Syst. Comput.
Mangal Deep Gupta, Rajeev K. Chauhan
2023 J jnl
Hardware Efficient Hybrid Pseudo-Random Bit Generator Using Coupled-LCG and Multistage LFSR with Clock Gating Network.
J. Circuits Syst. Comput.
Mangal Deep Gupta, Rajeev K. Chauhan, Sandeep Gulia
2022 J jnl
Hardware Efficient Pseudo-Random Number Generator Using Chen Chaotic System on FPGA.
J. Circuits Syst. Comput.
Mangal Deep Gupta, Rajeev K. Chauhan
2021 J jnl
Coupled variable-input LCG and clock divider-based large period pseudo-random bit generator on FPGA.
IET Comput. Digit. Tech.
Mangal Deep Gupta, Rajeev K. Chauhan
2021 J jnl
Efficient Hardware Implementation of Pseudo-Random Bit Generator Using Dual-CLCG Method.
J. Circuits Syst. Comput.
Mangal Deep Gupta, Rajeev K. Chauhan
2021 J jnl
Secure image encryption scheme using 4D-Hyperchaotic systems based reconfigurable pseudo-random number generator and S-Box.
Integr.
Mangal Deep Gupta, Rajeev K. Chauhan
2016 — conf
A compact tri-band BPF using meandered ring resonator.
RAIT
Priyanka Srivastava, Arvind Kumar Pandey, Rajeev K. Chauhan
2016 — conf
Performance Analysis of Fully Depleted SOI Tapered Body Reduced Source (FD-SOI TBRS) MOSFET for Low Power Digital Applications.
FICTA (2)
Vimal Kumar Mishra, Rajeev K. Chauhan
2016 — conf
Single notch band UWB BPF using square ring resonator.
RAIT
Yatindra Gaurav, Arvind Kumar Pandey, Rajeev K. Chauhan
2016 — conf
UWB BPF with Notch Band for Satellite Communication Using Pseudo-Interdigital Structure.
FICTA (1)
Yatindra Gaurav, Rajeev K. Chauhan
2014 — conf
Impact of Ge substrate on drain current of Trigate N-FinFET.
ICACCI
Vimal Kumar Mishra, Rajeev K. Chauhan
2008 J jnl
Effect of Ge profile design on the performance of an n-p-n SiGe HBT-based analog circuit.
Microelectron. J.
Ankit Kashyap, Rajeev K. Chauhan