| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2024 | J | jnl |
J. Circuits Syst. Comput.
|
| 2023 | J | jnl |
J. Circuits Syst. Comput.
|
| 2022 | J | jnl |
J. Circuits Syst. Comput.
|
| 2021 | J | jnl |
Coupled variable-input LCG and clock divider-based large period pseudo-random bit generator on FPGA.
IET Comput. Digit. Tech.
|
| 2021 | J | jnl |
J. Circuits Syst. Comput.
|
| 2021 | J | jnl |
Integr.
|
| 2016 | — | conf |
RAIT
|
| 2016 | — | conf |
FICTA (2)
|
| 2016 | — | conf |
RAIT
|
| 2016 | — | conf |
FICTA (1)
|
| 2014 | — | conf |
ICACCI
|
| 2008 | J | jnl |
Microelectron. J.
|