Rajasekhar Nagulapalli

31 papers C 4Misc 1Journal 12Unranked 14

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	A 2.9mW Inverter-based Quadrature Phase Clock Generator with ± 0.29° Phase Error. ISCAS Mayank Kumar Singh, M. Bhuvanesh, Rajasekhar Nagulapalli, Devarshi Mrinal Das, Mahendra Sakare
2024	—	`conf`	A 5.4mW 12GHz Quadrature VCO using current reusing technique in 28nm CMOS technology. ICCCNT Zahid Rashid Sheikh, Taranveer Kaur, Rajasekhar Nagulapalli, Hitesh Shrimali, Mahendra Sakare
2024	C	`conf`	A Wide Range Constant Transconductance Circuit Based on Negative Feedback for Analog Circuits. ISCAS Rakesh Kumar Palani, Srishti Agrawal, Ayan Alam Khan, Aadarsh V, Rajasekhar Nagulapalli
2023	—	`conf`	A Double Cross-Coupled Delay Cell for High-Frequency Differential Ring VCOs. APCCAS Mayank Kumar Singh, Manish Kumar Gautam, Puneet Singh, Rajasekhar Nagulapalli, Devarshi Mrinal Das, Mahendra Sakare
2023	J	`jnl`	A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency. J. Circuits Syst. Comput. Ravi Kumar, Rajasekhar Nagulapalli, Santosh Kumar Vishvakarma
2023	—	`conf`	Dynamic Averager Based Sub-1V Bandgap Voltage Reference. MWSCAS Rakesh Kumar Palani, Rajasekhar Nagulapalli, Srikar Bhagavatula
2022	C	`conf`	A Novel Sub-1V Bandgap Reference with 17.1 ppm/ ISCAS Rajasekhar Nagulapalli, Khaled Hayatleh, Nabil Yassine, S. Barker
2021	—	`conf`	8.7 A 112Gb/s ADC-DSP-Based PAM-4 Transceiver for Long-Reach Applications with >40dB Channel Loss in 7nm FinFET. ISSCC P. Mishra, Amber Tan, Belal Helal, Cheng-Ru Ho, C. Loi, Jamal Riani, J. Sun, Kaizad Mistry, Karthik Raviprakash, L. Tse, Mehdi Davoodi, M. Takefman, N. Fan, P. Prabha, Q. Liu, Q. Wang, Rajasekhar Nagulapalli, S. Cyrusian, S. Jantzi, S. Scouten, T. Dusatko, T. Setya, V. Giridharan, V. Gurumoorthy, Victor Karam, W. Liew, Y. Liao, Y. Ou
2021	C	`conf`	A 15uW, 12 ppm/ ISCAS Rajasekhar Nagulapalli, Rakesh Kumar Palani, Sweta Agarwal, Shouri Chatterjee, K. Hayatleh, S. Barker
2021	J	`jnl`	A 24.4 ppm/°C Voltage Mode Bandgap Reference With a 1.05V Supply. IEEE Trans. Circuits Syst. II Express Briefs Rajasekhar Nagulapalli, Rakesh Kumar Palani, Srikar Bhagavatula
2021	—	`conf`	A 82μW Mixed-Mode sub-1V Bandgap reference with 25 ppm/°C Temperature Co-efficient with Simultaneous PTAT Generation. VDAT T. R. Varun, Rajasekhar Nagulapalli, Immanuel Raja
2021	—	`conf`	A Novel 22.7 ppm/ MWSCAS Rajasekhar Nagulapalli, Rakesh Kumar Palani
2020	J	`jnl`	A High-Sensitivity and Low-Power Circuit for the Measurement of Abnormal Blood Cell Levels. J. Circuits Syst. Comput. Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Amr A. Tammam, F. John Lidgey, Nabil Yassine
2020	J	`jnl`	A Positive Feedback-Based Op-Amp Gain Enhancement Technique for High-Precision Applications. J. Circuits Syst. Comput. Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker
2020	—	`conf`	A Single BJT 10.2 ppm/°C Bandgap Reference in 45nm CMOS Technology. ICCCNT Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, B. Naresh Kumar Reddy
2020	J	`jnl`	A VGA Linearity Improvement Technique for ECG Analog Front-End in 65nm CMOS. J. Circuits Syst. Comput. Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker
2020	—	`conf`	A two-stage opamp frequency Compensation technique by splitting the 2 ICCCNT Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, B. Naresh Kumar Reddy
2019	J	`jnl`	A 0.55 V Bandgap Reference with a 59 ppm/°C Temperature Coefficient. J. Circuits Syst. Comput. Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Amr A. Tammam, Pantelis Georgiou, F. J. Lidgey
2019	J	`jnl`	A CMOS Self-Bias CTAT Current Generator with Improved Supply Sensitivity. J. Circuits Syst. Comput. Rajasekhar Nagulapalli
2019	—	`conf`	A High Frequency CMRR improvement technique for Differential Amplifiers in 45nm CMOS. ICCCNT Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, B. Naresh Kumar Reddy, B. Seetharamulu
2019	J	`jnl`	A High Value, Linear and Tunable CMOS Pseudo-Resistor for Biomedical Applications. J. Circuits Syst. Comput. Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Pantelis Georgiou, F. J. Lidgey
2019	J	`jnl`	A High-Performance Skin Impedance Measurement Circuit for Biomedical Applications. J. Circuits Syst. Comput. Khaled Hayatleh, Saddam Zourob, Rajasekhar Nagulapalli, Steve Barker, Nabil Yassine, Pantelis Georgiou, F. J. Lidgey
2019	J	`jnl`	A Low Noise Amplifier Suitable for Biomedical Recording Analog Front-End in 65nm CMOS Technology. J. Circuits Syst. Comput. Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Amr A. Tammam, Nabil Yassine, Bilal Yassine, Mohamed Ben-Esmael
2019	—	`conf`	A Low Power Miller Compensation Technique for Two Stage Op-amp in 65nm CMOS Technology. ICCCNT Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, B. Naresh Kumar Reddy, B. Seetharamulu
2019	J	`jnl`	A Start-up Assisted Fully Differential Folded Cascode Opamp. J. Circuits Syst. Comput. Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Bilal Yassine, Saddam Zourob, Sumathi Raparthy, Nabil Yassine
2018	J	`jnl`	A 0.6 V MOS-Only Voltage Reference for Biomedical Applications with 40 ppm/∘C Temperature Drift. J. Circuits Syst. Comput. Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Sumathi Raparthy, Nabil Yassine, John Lidgey
2018	—	`conf`	A 31 ppm/° C Pure CMOS Bandgap Reference by Exploiting Beta-Multiplier. VDAT Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Saddam Zourob, Nabil Yassine, B. Naresh Kumar Reddy
2018	—	`conf`	A Technique to Reduce the Capacitor Size in Two Stage Miller Compensated Opamp. ICCCNT Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Saddam Zourob, Nabil Yassine, B. Naresh Kumar Reddy
2018	—	`conf`	High Performance Circuit Techniques for Nueral Front-End Design in 65nm CMOS. ICCCNT Rajasekhar Nagulapalli, Khaled Hayatleh, Steve Barker, Saddam Zourob, Nabil Yassine, B. Naresh Kumar Reddy
2016	—	`conf`	23.5 A dual 64Gbaud 10kΩ 5% THD linear differential transimpedance amplifier with automatic gain control in 0.13µm BiCMOS technology for optical fiber coherent receivers. ISSCC Ahmed Awny, Rajasekhar Nagulapalli, Daniel Micusik, Jan Hoffmann, Gunter Fischer, Dietmar Kissinger, Ahmet Cagri Ulusoy
2010	Misc	`conf`	High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique. VLSI Design Kunal Desai, Rajasekhar Nagulapalli, Vijay Krishna, Rajkumar Palwai, Pravin Kumar Venkatesan, Vijay Khawshe