Rajaraman Ramanarayanan

11 papers C 1Misc 3Journal 1Unranked 6
YearRankTypeTitle / Venue / Authors
2013 C conf
Split-Path Fused Floating Point Multiply Accumulate (FPMAC).
IEEE Symposium on Computer Arithmetic
Suresh Srinivasan, Ketan Bhudiya, Rajaraman Ramanarayanan, P. Sahit Babu, Tiju Jacob, Sanu Mathew, Ram Krishnamurthy, Vasantha Erraguntla
2012 — conf
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS.
ISSCC
Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar
2012 — conf
An IA-32 processor with a wide voltage operating range in 32nm CMOS.
Hot Chips Symposium
Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar
2010 — conf
18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS.
ESSCIRC
Rajaraman Ramanarayanan, Sanu Mathew, Farhana Sheikh, Suresh Srinivasan, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Vasantha Erraguntla, Ram Krishnamurthy
2010 — conf
A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS.
ISSCC
Amit Agarwal, Sanu Mathew, Steven Hsu, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar
2009 J jnl
Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits.
IEEE Trans. Dependable Secur. Comput.
Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu
2008 Misc conf
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores.
VLSI Design
Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron
2007 Misc conf
A Process Scheduler-Based Approach to NoC Power Management.
VLSI Design
Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaköy, Rajaraman Ramanarayanan, Balaji Vaidyanathan
2007 Misc conf
Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors.
VLSI Design
Liping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk, Rajaraman Ramanarayanan, Balaji Vaidyanathan
2004 — conf
The Effect of Threshold Voltages on the Soft Error Rate.
ISQED
Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin
2003 — conf
Effect of Power Optimizations on Soft Error Rate.
VLSI-SoC (Selected Papers)
Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin