Rainer Schaffer

17 papers B 2C 2Misc 1Journal 3Unranked 8
YearRankTypeTitle / Venue / Authors
2024 J jnl
Assessment and Level Modelling in Fundamentals of Electrical Engineering.
Int. J. Eng. Pedagog.
Alison Klein, Jens Müller, Nico Link, Rainer Schaffer
2012 B conf
Administration- and communication-aware IP core mapping in scalable multiprocessor system-on-chips via evolutionary computing.
IEEE Congress on Evolutionary Computation
Falko Guderian, Rainer Schaffer, Gerhard P. Fettweis
2012 B conf
Dimensioning the heterogeneous multicluster architecture via parallelism analysis and evolutionary computing.
IEEE Congress on Evolutionary Computation
Falko Guderian, Rainer Schaffer, Gerhard P. Fettweis
2010 — —
Parallelisierung von Algorithmen zur Nutzung auf Architekturen mit Teilwortparallelität.
Rainer Schaffer
2008 C conf
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism.
DSD
Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich
2007 — conf
Massively Parallel Processor Architectures: A Co-design Approach.
ReCoSoC
Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier
2006 — conf
An Architecture Description Language for Massively Parallel Processor Architectures.
MBMV
Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker
2006 — conf
Derivation of Packing Instructions for Exploiting Sub-Word Parallelism.
PARELEC
Rainer Schaffer, Renate Merker, Francky Catthoor
2006 — conf
Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels.
PARELEC
Sebastian Siegel, Rainer Schaffer, Renate Merker
2006 — conf
Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism.
ICSAMOS
Rainer Schaffer, Renate Merker
2005 — conf
Co-Design of Massively Parallel Embedded Processor Architectures.
ReCoSoC
Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys
2004 — conf
A Parallel Hardware-Software System for Signal Processing Algorithms.
PARELEC
Mathias Kortke, Jan Müller, Rainer Schaffer, Sebastian Siegel, Renate Merker, Jürgen Kelber
2003 J jnl
A Hardware-Software System for Tomographic Reconstruction.
J. Circuits Syst. Comput.
Jan Müller, Dirk Fimmel, Renate Merker, Rainer Schaffer
2003 C conf
Causality Constraints for Processor Architectures with Sub-Word Parallelism.
DSD
Rainer Schaffer, Renate Merker, Francky Catthoor
2002 — conf
Systematic Design of Programs with Sub-Word Parallelism.
PARELEC
Rainer Schaffer, Renate Merker, Francky Catthoor
2000 Misc conf
Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel.
VLSI Design
Rainer Schaffer, Renate Merker, Francky Catthoor
2000 J jnl
Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel.
Parallel Algorithms Appl.
Rainer Schaffer, Francky Catthoor, Renate Merker