Rainer Leupers

380 papers A* 16A 53B 7C 35Misc 24Journal 101Unranked 132

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Mixed-Precision Training and Compilation for RRAM-based Computing-in-Memory Accelerators. CoRR Rebecca Pelke, Joel Klein, José Cubero-Cascante, Nils Bosbach, Jan Moritz Joseph, Rainer Leupers
2026	J	`jnl`	NQC2: A Non-Intrusive QEMU Code Coverage Plugin. CoRR Nils Bosbach, Alwalid Salama, Lukas Jünger, Mark Burton, Niko Zurstraßen, Rebecca Pelke, Rainer Leupers
2025	A	`conf`	Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors. ICCAD Evgenii Rezunov, Niko Zurstraßen, Lennart M. Reimann, Rainer Leupers
2025	J	`jnl`	Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors. CoRR Evgenii Rezunov, Niko Zurstraßen, Lennart M. Reimann, Rainer Leupers
2025	J	`jnl`	Bridging the Gap: Physical PCI Device Integration Into SystemC-TLM Virtual Platforms. CoRR Nils Bosbach, Rebecca Pelke, Niko Zurstraßen, Jan Henrik Weinstock, Lukas Jünger, Rainer Leupers
2025	J	`jnl`	CIMFlow: Modelling Dataflow in Cross-Layer Compute-in-Memory Deep Learning Accelerators. ACM Trans. Embed. Comput. Syst. José Cubero-Cascante, Lucas Tonini Rosenberg Schneider, Rebecca Pelke, Arunkumar Vaidyanathan, Rainer Leupers, Jan Moritz Joseph
2025	—	`conf`	EXAMINER: IP Extraction Algorithm from MAGIC Logic-in-Memory. ISVLSI Lorenzo Pfeifer, Rainer Leupers, Jan Moritz Joseph
2025	—	`conf`	Evaluating the Scalability of Binary and Ternary CNN Workloads on RRAM-based Compute-in-Memory Accelerators. ISVLSI José Cubero-Cascante, Rebecca Pelke, Noah Flohr, Arunkumar Vaidyanathan, Rainer Leupers, Jan Moritz Joseph
2025	J	`jnl`	FMI Meets SystemC: A Framework for Cross-Tool Virtual Prototyping. CoRR Nils Bosbach, Meik Schmidt, Lukas Jünger, Matthias Berthold, Rainer Leupers
2025	A	`conf`	FloppyFloat: An Open Source Floating Point Library for Instruction Set Simulators. DATE Niko Zurstraßen, Nils Bosbach, Rainer Leupers
2025	A	`conf`	High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms. DATE Nils Bosbach, Rebecca Pelke, Niko Zurstraßen, Jan Henrik Weinstock, Lukas Jünger, Rainer Leupers
2025	J	`jnl`	High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms. CoRR Nils Bosbach, Rebecca Pelke, Niko Zurstraßen, Jan Henrik Weinstock, Lukas Jünger, Rainer Leupers
2025	A*	`conf`	Introducing Instruction-Accurate Simulators for Performance Estimation of Autotuning Workloads. DAC Rebecca Pelke, Nils Bosbach, Lennart M. Reimann, Rainer Leupers
2025	J	`jnl`	Introducing Instruction-Accurate Simulators for Performance Estimation of Autotuning Workloads. CoRR Rebecca Pelke, Nils Bosbach, Lennart M. Reimann, Rainer Leupers
2025	J	`jnl`	It's Getting Hot in Here: Hardware Security Implications of Thermal Crosstalk on ReRAMs. IEEE Trans. Reliab. Felix Staudigl, Hazem Al Indari, Daniel Schön, Hsin-Yu Chen, Dominik Sisejkovic, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Amelie Hagelauer, Rainer Leupers
2025	J	`jnl`	Leveraging SystemC-TLM-based Virtual Prototypes for Embedded Software Fuzzing. CoRR Chiara Ghinami, Jonas Winzer, Nils Bosbach, Lennart M. Reimann, Lukas Jünger, Simon Wörner, Rainer Leupers
2025	J	`jnl`	Optimizing Binary and Ternary Neural Network Inference on RRAM Crossbars using CIM-Explorer. CoRR Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Niklas Degener, Florian Idrizi, Lennart M. Reimann, Jan Moritz Joseph, Rainer Leupers
2025	—	`conf`	Rapid RISC-V Floating Point Vector Simulation. RAPIDO@HiPEAC Niko Zurstraßen, Nils Bosbach, Lukas Jünger, Rainer Leupers
2025	A	`conf`	Static Global Register Allocation for Dynamic Binary Translators. DATE Niko Zurstraßen, Nils Bosbach, Lennart M. Reimann, Rainer Leupers
2025	—	`conf`	The Impact of Logic Locking on Confidentiality: An Automated Evaluation. ISQED Lennart M. Reimann, Evgenii Rezunov, Dominik Germek, Luca Collini, Christian Pilato, Ramesh Karri, Rainer Leupers
2025	J	`jnl`	The Impact of Logic Locking on Confidentiality: An Automated Evaluation. CoRR Lennart M. Reimann, Evgenii Rezunov, Dominik Germek, Luca Collini, Christian Pilato, Ramesh Karri, Rainer Leupers
2025	J	`jnl`	The art of temporal decoupling. Integr. Niko Zurstraßen, Ruben Brandhofer, José Cubero-Cascante, Nils Bosbach, Lukas Jünger, Rainer Leupers
2024	—	`conf`	A Calibratable Model for Fast Energy Estimation of MVM Operations on RRAM Crossbars. AICAS José Cubero-Cascante, Arunkumar Vaidyanathan, Rebecca Pelke, Lorenzo Pfeifer, Rainer Leupers, Jan Moritz Joseph
2024	—	`conf`	A Fully Automated Platform for Evaluating ReRAM Crossbars. LATS Rebecca Pelke, Felix Staudigl, Niklas Thomas, Nils Bosbach, Mohammed Hossein, José Cubero-Cascante, Letícia Maria Veiras Bolzani, Rainer Leupers, Jan Moritz Joseph
2024	J	`jnl`	A Fully Automated Platform for Evaluating ReRAM Crossbars. CoRR Rebecca Pelke, Felix Staudigl, Niklas Thomas, Nils Bosbach, Mohammed Hossein, José Cubero-Cascante, Leticia Bolzani Poehls, Rainer Leupers, Jan Moritz Joseph
2024	—	`conf`	Analysis of Thermal Side-Channel Attacks on Analog/Digital Computing-in-Memory Accelerators. LATS Lorenzo Pfeifer, M. Gross, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph
2024	A	`conf`	CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures. DATE Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph
2024	J	`jnl`	CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures. CoRR Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph
2024	J	`jnl`	Exploiting the Lock: Leveraging MiG-V's Logic Locking for Secret-Data Extraction. CoRR Lennart M. Reimann, Yadu Madhukumar Variyar, Lennet Huelser, Chiara Ghinami, Dominik Germek, Rainer Leupers
2024	—	`conf`	NQC²: A Non-Intrusive QEMU Code Coverage Plugin. RAPIDO@HiPEAC Nils Bosbach, Alwalid Salama, Lukas Jünger, Mark Burton, Niko Zurstraßen, Rebecca Pelke, Rainer Leupers
2024	—	`conf`	NVM-Flip: Non-Volatile-Memory BitFlips on the System Level. SAT-CPS@CODASPY Felix Staudigl, Jan Philipp Thoma, Christian Niesler, Karl J. X. Sturm, Rebecca Pelke, Dominik Germek, Jan Moritz Joseph, Tim Güneysu, Lucas Davi, Rainer Leupers
2024	J	`jnl`	ProMiSE: A Programmable Hardware Monitor for Secure Execution in Zero Trust Networks. IEEE Embed. Syst. Lett. Nikhilesh Singh, Shagnik Pal, Rainer Leupers, Farhad Merchant, Chester Rebeiro
2024	J	`jnl`	QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL. CoRR Lennart M. Reimann, Anschul Prashar, Chiara Ghinami, Rebecca Pelke, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2024	B	`conf`	Spiking Neural Networks for Signal Classification with Digital and Analog Neuromorphic Systems: A Comparative Study. IJCNN Leon Happek, Jen-Tse Huang, Alejandro Garcia Gener, Rainer Leupers, Melvin Galicia
2024	B	`conf`	The Optimal Quantum of Temporal Decoupling. ASPDAC Niko Zurstraßen, Ruben Brandhofer, José Cubero-Cascante, Nils Bosbach, Lukas Jünger, Rainer Leupers
2024	A*	`conf`	Towards High-Performance Virtual Platforms: A Parallelization Strategy for SystemC TLM-2.0 CPU Models. DAC Nils Bosbach, Niko Zurstraßen, Rebecca Pelke, Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers
2024	J	`jnl`	veriSIMPLER: An Automated Formal Verification Methodology for SIMPLER MAGIC Design Style Based In-Memory Computing. IEEE Trans. Circuits Syst. I Regul. Pap. Chandan Kumar Jha, Khushboo Qayyum, Kemal Çaglar Coskun, Simranjeet Singh, Muhammad Hassan, Rainer Leupers, Farhad Merchant, Rolf Drechsler
2023	—	`conf`	"S3cure": Scramble, Shuffle and Shambles - Secure Deployment of Weight Matrices in Memristor Crossbar Arrays. ICONS Melvin Estuardo Galicia, Ibrahim Jimale Osman, Christian Owusu-Afriyie, Rainer Leupers
2023	—	`conf`	Architecture-Compiler Co-design for ReRAM-Based Multi-core CIM Architectures. VLSI-SoC (Selected Papers) Rebecca Pelke, Nils Bosbach, Niklas Degener, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph
2023	—	`conf`	Automated Information Flow Analysis for Integrated Computing-in-Memory Modules. NEWCAS Lennart M. Reimann, Felix Staudigl, Rainer Leupers
2023	J	`jnl`	Automated Information Flow Analysis for Integrated Computing-in-Memory Modules. CoRR Lennart M. Reimann, Felix Staudigl, Rainer Leupers
2023	J	`jnl`	CLARINET: A quire-enabled RISC-V-based framework for posit arithmetic empiricism. J. Syst. Archit. Niraj N. Sharma, Riya Jain, Mohana Madhumita Pokkuluri, Sachin B. Patkar, Rainer Leupers, Rishiyur S. Nikhil, Farhad Merchant
2023	C	`conf`	Efficient RISC-V-on-x64 Floating Point Simulation. ICCD Niko Zurstraßen, Nils Bosbach, Jan Moritz Joseph, Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers
2023	—	`conf`	Enhancing HW-SW Confidentiality Verification for Embedded Processors with SoftFlow's Advanced Memory Range Feature. VLSI-SoC (Selected Papers) Lennart M. Reimann, Jonathan Wiesner, Karol Jaszczyk, Chiara Ghinami, Dominik Germek, Farhad Merchant, Rainer Leupers
2023	—	`conf`	Entropy-Based Analysis of Benchmarks for Instruction Set Simulators. DroneSE/RAPIDO@HiPEAC Nils Bosbach, Lukas Jünger, Rebecca Pelke, Niko Zurstraßen, Rainer Leupers
2023	—	`conf`	Exploring Multi-Valued Logic and its Application in Emerging Post-CMOS Technologies. NANOARCH Simranjeet Singh, Elmira Moussavi, Christopher Bengel, Sachin B. Patkar, Rainer Waser, Rainer Leupers, Vikas Rana, Vivek Pachauri, Stephan Menzel, Farhad Merchant
2023	A*	`conf`	Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. DAC Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers
2023	J	`jnl`	Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. CoRR Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Leticia Bolzani Poehls, Rainer Leupers
2023	—	`conf`	Frequency and noise characterization for baseband signal processing on neuromorphic circuits. NEWCAS Melvin Galicia, Leon Happek, Magnus Balzer, Rainer Leupers
2023	—	`conf`	Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. NEWCAS Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant
2023	J	`jnl`	Gate Camouflaging Using Reconfigurable ISFET-Based Threshold Voltage Defined Logic. CoRR Elmira Moussavi, Animesh Singh, Dominik Sisejkovic, Aravind Padma Kumar, Daniyar Kizatov, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant
2023	—	`conf`	Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware. LATS Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Veiras Bolzani Poehls, Rainer Leupers
2023	C	`conf`	Mapping of CNNs on multi-core RRAM-based CIM architectures. VLSI-SoC Rebecca Pelke, Nils Bosbach, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph
2023	J	`jnl`	Mapping of CNNs on multi-core RRAM-based CIM architectures. CoRR Rebecca Pelke, Nils Bosbach, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph
2023	—	`conf`	Quantitative Information Flow for Hardware: Advancing the Attack Landscape. LASCAS Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers
2023	C	`conf`	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. VLSI-SoC Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2023	J	`jnl`	SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors. CoRR Lennart M. Reimann, Jonathan Wiesner, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2023	Misc	`conf`	Work-in-Progress: A Generic Non-Intrusive Parallelization Approach for SystemC TlM-2.0-Based Virtual Platforms. CODES+ISSS Nils Bosbach, Rebecca Pelke, Niko Zurstraßen, Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers
2023	Misc	`conf`	Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. CODES+ISSS Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers
2023	J	`jnl`	Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. CoRR Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers
2023	A	`conf`	ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous Driving. DATE Gia Bao Thieu, Sven Gesper, Guillermo Payá-Vayá, Christoph Riggers, Oliver Renke, Till Fiedler, Jakob Marten, Tobias Stuckenberg, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart M. Reimann, Rainer Leupers, Michael Beyer, Daniel Köhler, Alisa Jauch, Jan Micha Borrmann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Blüthgen, Christian Sauer
2023	A	`conf`	par-gem5: Parallelizing gem5's Atomic Mode. DATE Niko Zurstraßen, José Cubero-Cascante, Jan Moritz Joseph, Li Yichao, Xinghua Xie, Rainer Leupers
2023	—	`conf`	parti-gem5: gem5's Timing Mode Parallelised. SAMOS José Cubero-Cascante, Niko Zurstraßen, Jörn Nöller, Rainer Leupers, Jan Moritz Joseph
2023	J	`jnl`	parti-gem5: gem5's Timing Mode Parallelised. CoRR José Cubero-Cascante, Niko Zurstraßen, Jörn Nöller, Rainer Leupers, Jan Moritz Joseph
2022	—	`conf`	A Parallel SystemC Virtual Platform for Neuromorphic Architectures. ISQED Melvin Galicia, Farhad Merchant, Rainer Leupers
2022	J	`jnl`	A Survey of Neuromorphic Computing-in-Memory: Architectures, Simulators, and Security. IEEE Des. Test Felix Staudigl, Farhad Merchant, Rainer Leupers
2022	—	`conf`	A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. LATS Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant
2022	J	`jnl`	A Temperature Independent Readout Circuit for ISFET-Based Sensor Applications. CoRR Elmira Moussavi, Dominik Sisejkovic, Animesh Singh, Daniyar Kizatov, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant
2022	J	`jnl`	AMAIX In-Depth: A Generic Analytical Model for Deep Learning Accelerators. Int. J. Parallel Program. Niko Zurstraßen, Lukas Jünger, Tim Kogel, Holger Keding, Rainer Leupers
2022	J	`jnl`	Deceptive Logic Locking for Hardware Integrity Protection Against Machine Learning Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers
2022	—	`conf`	Design and Exploration of an ARC-Coprocessor for LSTM Based Audio Applications. NorCAS Sebastian Birke, Bjoern Hartmann, Dominik Auras, Markus Wloka, Gerd Ascheid, Rainer Leupers
2022	J	`jnl`	Designing ML-Resilient Locking at Register-Transfer Level. CoRR Dominik Sisejkovic, Luca Collini, Benjamin Tan, Christian Pilato, Ramesh Karri, Rainer Leupers
2022	A*	`conf`	Designing ML-resilient locking at register-transfer level. DAC Dominik Sisejkovic, Luca Collini, Benjamin Tan, Christian Pilato, Ramesh Karri, Rainer Leupers
2022	B	`conf`	EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs. FPL Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph
2022	J	`jnl`	EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs. CoRR Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph
2022	A	`conf`	NEUROTEC I: Neuro-inspired Artificial Intelligence Technologies for the Electronics of the Future. DATE Melvin Galicia, Stephan Menzel, Farhad Merchant, Maximilian Müller, Hsin-Yu Chen, Qing-Tai Zhao, Felix Cüppers, Abdur R. Jalil, Qi Shu, Peter Schüffelgen, Gregor Mussler, Carsten Funck, Christian Lanius, Stefan Wiefels, Moritz von Witzleben, Christopher Bengel, Nils Kopperberg, Tobias Ziegler, R. Walied Ahmad, Alexander Krüger, Letícia Maria Bolzani Pöhls, Regina Dittmann, Susanne Hoffmann-Eifert, Vikas Rana, Detlev Grützmacher, Matthias Wuttig, Dirk J. Wouters, Andrei Vescan, Tobias Gemmeke, Joachim Knoch, Max Christian Lemme, Rainer Leupers, Rainer Waser
2022	C	`conf`	NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool. VLSI-SoC Nils Bosbach, Jan Moritz Joseph, Rainer Leupers, Lukas Jünger
2022	J	`jnl`	NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool. CoRR Nils Bosbach, Lukas Jünger, Jan Moritz Joseph, Rainer Leupers
2022	A	`conf`	NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. DATE Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers
2022	C	`conf`	PA-PUF: A Novel Priority Arbiter PUF. VLSI-SoC Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant
2022	J	`jnl`	PA-PUF: A Novel Priority Arbiter PUF. CoRR Simranjeet Singh, Srinivasu Bodapati, Sachin B. Patkar, Rainer Leupers, Anupam Chattopadhyay, Farhad Merchant
2022	J	`jnl`	Quantitative Information Flow for Hardware: Advancing the Attack Landscape. CoRR Lennart M. Reimann, Sarp Erdönmez, Dominik Sisejkovic, Rainer Leupers
2022	—	`conf`	Virtual Platform Acceleration through Userspace Host Execution. SOCC Lukas Jünger, Antonios Salios, Peter Blöcher, Rainer Leupers
2022	—	`conf`	X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. AICAS Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers
2022	J	`jnl`	X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. CoRR Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers
2022	C	`conf`	X-on-X: Distributed Parallel Virtual Platforms for Heterogeneous Systems. DSD Lukas Jünger, Simon Winther, Rainer Leupers
2022	—	`conf`	pHGen: A pH-Based Key Generation Mechanism Using ISFETs. HOST Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu, Rainer Leupers, Sven Ingebrandt, Vivek Pachauri, Farhad Merchant
2022	J	`jnl`	pHGen: A pH-Based Key Generation Mechanism Using ISFETs. CoRR Elmira Moussavi, Dominik Sisejkovic, Fabian Brings, Daniyar Kizatov, Animesh Singh, Xuan Thang Vu, Sven Ingebrandt, Rainer Leupers, Vivek Pachauri, Farhad Merchant
2021	J	`jnl`	A Parallel SystemC Virtual Platform for Neuromorphic Architectures. CoRR Melvin Galicia, Farhad Merchant, Rainer Leupers
2021	Misc	`conf`	ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. VLSID Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers
2021	J	`jnl`	ANDROMEDA: An FPGA Based RISC-V MPSoC Exploration Framework. CoRR Farhad Merchant, Dominik Sisejkovic, Lennart M. Reimann, Kirthihan Yasotharan, Thomas Grass, Rainer Leupers
2021	Misc	`conf`	An Investigation on Inherent Robustness of Posit Data Representation. VLSID Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant, Rainer Leupers
2021	J	`jnl`	An Investigation on Inherent Robustness of Posit Data Representation. CoRR Ihsen Alouani, Anouar Ben Khalifa, Farhad Merchant, Rainer Leupers
2021	—	`conf`	Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. ISQED Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna
2021	—	`conf`	Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures. ASP-DAC Jan Moritz Joseph, Lennart Bamberg, Geonhwa Jeong, Ruei-Ting Chien, Rainer Leupers, Alberto García-Ortiz, Tushar Krishna, Thilo Pionteck
2021	—	`conf`	Brightening the Optical Flow through Posit Arithmetic. ISQED Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer, John L. Gustafson, Sangeeth Nambiar, Rainer Leupers, Farhad Merchant
2021	J	`jnl`	Brightening the Optical Flow through Posit Arithmetic. CoRR Vinay Saxena, Ankitha Reddy, Jonathan Neudorfer, John L. Gustafson, Sangeeth Nambiar, Rainer Leupers, Farhad Merchant
2021	J	`jnl`	Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. ACM J. Emerg. Technol. Comput. Syst. Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers
2021	J	`jnl`	ConvAix: An Application-Specific Instruction-Set Processor for the Efficient Acceleration of CNNs. IEEE Open J. Circuits Syst. Andreas Bytyn, Rainer Leupers, Gerd Ascheid
2021	J	`jnl`	Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks. CoRR Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers
2021	C	`conf`	Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. VLSI-SoC Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers
2021	J	`jnl`	Logic Locking at the Frontiers of Machine Learning: A Survey on Developments and Opportunities. CoRR Dominik Sisejkovic, Lennart M. Reimann, Elmira Moussavi, Farhad Merchant, Rainer Leupers
2021	—	`conf`	NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI. NOCS Jan Moritz Joseph, Murat Sezgin Baloglu, Yue Pan, Rainer Leupers, Lennart Bamberg
2021	A	`conf`	Nano Security: From Nano-Electronics to Secure Systems. DATE Ilia Polian, Frank Altmann, Tolga Arul, Christian Boit, Ralf Brederlow, Lucas Davi, Rolf Drechsler, Nan Du, Thomas Eisenbarth, Tim Güneysu, Sascha Hermann, Matthias Hiller, Rainer Leupers, Farhad Merchant, Thomas Mussenbrock, Stefan Katzenbeisser, Akash Kumar, Wolfgang Kunz, Thomas Mikolajick, Vivek Pachauri, Jean-Pierre Seifert, Frank Sill Torres, Jens Trommer
2021	J	`jnl`	NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. CoRR Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers
2021	—	`conf`	NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic Accelerators. SoCC Melvin Galicia, Ali BanaGozar, Karl J. X. Sturm, Felix Staudigl, Sander Stuijk, Henk Corporaal, Rainer Leupers
2021	—	`conf`	Optimizing Temporal Decoupling using Event Relevance. ASP-DAC Lukas Jünger, Carmine Bianco, Kristof Niederholtmeyer, Dietmar Petras, Rainer Leupers
2021	C	`conf`	QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. ICCD Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2021	J	`jnl`	QFlow: Quantitative Information Flow for Security-Aware Hardware Design in Verilog. CoRR Lennart M. Reimann, Luca Hanel, Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2021	C	`conf`	Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging Nondeterminism. DSD Milan Copic, Rainer Leupers, Gerd Ascheid
2021	—	`conf`	Software-defined Temporal Decoupling in Virtual Platforms. SoCC Lukas Jünger, Alexander Belke, Rainer Leupers
2021	C	`conf`	Trustworthy Hardware Design with Logic Locking. VLSI-SoC Dominik Sisejkovic, Rainer Leupers
2020	—	`conf`	3D Optimisation of Software Application Mappings on Heterogeneous MPSoCs. ARCS Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse
2020	C	`conf`	A secure hardware-software solution based on RISC-V, logic locking and microkernel. SCOPES Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Massimiliano Giacometti, Sascha Kegreiß
2020	—	`conf`	AMAIX: A Generic Analytical Model for Deep Learning Accelerators. SAMOS Lukas Jünger, Niko Zurstraßen, Tim Kogel, Holger Keding, Rainer Leupers
2020	A	`conf`	ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual Platforms. DATE Lukas Jünger, Jan Luca Malte Bölke, Stephan Tobies, Rainer Leupers, Andreas Hoffmann
2020	J	`jnl`	Accelerating Deep Learning Inference in Constrained Embedded Devices Using Hardware Loops and a Dot Product Unit. IEEE Access Jure Vreca, Karl J. X. Sturm, Ernest Gungl, Farhad Merchant, Paolo Bientinesi, Rainer Leupers, Zmago Brezocnik
2020	J	`jnl`	Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. CoRR Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna
2020	J	`jnl`	CLARINET: A RISC-V Based Framework for Posit Arithmetic Empiricism. CoRR Riya Jain, Niraj N. Sharma, Farhad Merchant, Sachin B. Patkar, Rainer Leupers
2020	J	`jnl`	Challenging the Security of Logic Locking Schemes in the Era of Deep Learning: A Neuroevolutionary Approach. CoRR Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Harshit Srivastava, Ahmed Hallawa, Rainer Leupers
2020	J	`jnl`	Dataflow Aware Mapping of Convolutional Neural Networks Onto Many-Core Platforms With Network-on-Chip Interconnect. CoRR Andreas Bytyn, René Ahlsdorf, Rainer Leupers, Gerd Ascheid
2020	A	`conf`	Modelling Machine Learning Components for Mapping and Scheduling of AUTOSAR Runnables. ISSRE Milan Copic, Rainer Leupers, Gerd Ascheid
2020	A	`conf`	Next Generation Arithmetic for Edge Computing. DATE Andre Guntoro, Cecilia De la Parra, Farhad Merchant, Florent de Dinechin, John L. Gustafson, Martin Langhammer, Rainer Leupers, Sangeeth Nambiar
2020	J	`jnl`	Reducing idle time in event-triggered software execution via runnable migration and DPM-Aware scheduling. Integr. Milan Copic, Rainer Leupers, Gerd Ascheid
2020	—	`conf`	Scaling Logic Locking Schemes to Multi-module Hardware Designs. ARCS Dominik Sisejkovic, Farhad Merchant, Lennart M. Reimann, Rainer Leupers, Sascha Kegreiß
2019	—	`conf`	A Critical Evaluation of the Paradigm Shift in the Design of Logic Encryption Algorithms. VLSI-DAT Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Volker Kiefer
2019	Misc	`conf`	A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design. VLSID Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
2019	—	`conf`	A heuristic for multi objective software application mappings on heterogeneous MPSoCs. ASP-DAC Gereon Onnebrink, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Awaid-Ud-Din Shaheen
2019	C	`conf`	An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. ISCAS Andreas Bytyn, Rainer Leupers, Gerd Ascheid
2019	J	`jnl`	An Application-Specific VLIW Processor with Vector Instruction Set for CNN Acceleration. CoRR Andreas Bytyn, Rainer Leupers, Gerd Ascheid
2019	Misc	`conf`	Applying Modified Householder Transform to Kalman Filter. VLSID Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
2019	J	`jnl`	Automatic Energy-Minimized HW/SW Partitioning for FPGA-Accelerated MPSoCs. IEEE Embed. Syst. Lett. Gereon Führ, Seyit Halil Hamurcu, Diego Pala, Thomas Grass, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse
2019	—	`conf`	Combined MPSoC Task Mapping and Memory Optimization for Low-Power. APCCAS Manuel Strobel, Gereon Führ, Martin Radetzki, Rainer Leupers
2019	—	`conf`	Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans. ACM Great Lakes Symposium on VLSI Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss
2019	—	`conf`	Efficient sporadic task handling in parallel AUTOSAR applications using runnable migration. ASP-DAC Milan Copic, Rainer Leupers, Gerd Ascheid
2019	—	`conf`	Fast SystemC Processor Models with Unicorn. RAPIDO Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid
2019	B	`conf`	Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries. ETS Dominik Sisejkovic, Farhad Merchant, Rainer Leupers, Gerd Ascheid, Sascha Kegreiss
2019	J	`jnl`	Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA. Integr. Gereon Führ, Ahmed Hallawa, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse
2019	—	`conf`	Protecting the Integrity of Processor Cores with Logic Encryption. SoCC Dominik Sisejkovic, Farhad Merchant, Rainer Leupers
2019	Misc	`conf`	VLSI Architectures for ORVD Trellis based MIMO Detection. ICNC Sebastian Birke, Dominik Auras, Tobias Piwczyk, Robin Mahlke, Nikolas Alberti, Rainer Leupers, Gerd Ascheid
2018	—	`conf`	A Multi-domain Co-simulation Ecosystem for Fully Virtual Rapid ADAS Prototyping. SMARTGREENS/VEHITS (Selected Papers) Robert Lajos Bücs, Pramod Lakshman, Jan Henrik Weinstock, Florian Walbroel, Rainer Leupers, Gerd Ascheid
2018	—	`conf`	A Unifying logic encryption security metric. SAMOS Dominik Sisejkovic, Rainer Leupers, Gerd Ascheid, Simon Metzner
2018	Misc	`conf`	AMVP - a high performance virtual platform using parallel systemC for multicore ARM architectures: work-in-progress. CODES+ISSS Jan Henrik Weinstock, Robert Lajos Bücs, Florian Walbroel, Rainer Leupers, Gerd Ascheid
2018	—	`conf`	ESL Black Box Power Estimation: Automatic Calibration for IEEE UPF 3.0 Power Models. RAPIDO Gereon Onnebrink, Rainer Leupers, Gerd Ascheid
2018	J	`jnl`	Efficient Realization of Givens Rotation through Algorithm-Architecture Co-design for Acceleration of QR Factorization. CoRR Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
2018	C	`conf`	Fully Virtual Rapid ADAS Prototyping via a Joined Multi-domain Co-simulation Ecosystem. VEHITS Robert Lajos Bücs, Pramod Lakshman, Jan Henrik Weinstock, Florian Walbroel, Rainer Leupers, Gerd Ascheid
2018	—	`conf`	HiPEAC compilation architecture. MECO Koen De Bosschere, Rainer Leupers
2018	—	`conf`	Multi-Scale Code Generation for Simulation-Driven Rapid ADAS Prototyping: the SMELT Approach. ICVES Robert Lajos Bücs, Marcel Heistermann, Rainer Leupers, Gerd Ascheid
2018	—	`conf`	Multi-Scale Multi-Domain Co-Simulation for Rapid ADAS Prototyping. APCCAS Robert Lajos Bücs, Rainer Leupers, Gerd Ascheid
2018	A	`conf`	OHEX: OS-aware hybridization techniques for accelerating MPSoC full-system simulation. DATE Robert Lajos Bücs, Maximilian Fricke, Rainer Leupers, Gerd Ascheid, Stephan Tobies, Andreas Hoffmann
2018	C	`conf`	Parameterized Posit Arithmetic Hardware Generator. ICCD Rohit Chaurasiya, John L. Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers
2018	Misc	`conf`	Reducing the Computational Complexity of ORVD-Trellis Search Based MIMO Detection. ICNC Dominik Auras, Sebastian Birke, Rainer Leupers, Gerd Ascheid
2018	—	`conf`	VLSI implementation of channel estimation for millimeter wave beamforming training. LASCAS Sebastian Birke, Wei-Jhe Chen, Gaojian Wang, Dominik Auras, Chung-An Shen, Rainer Leupers, Gerd Ascheid
2017	—	`conf`	Accelerating MPSoC Simulation Using Parallel SystemC and Processor Sleep Models. RAPIDO Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid
2017	—	`conf`	DVFS-enabled power-performance trade-off in MPSoC SW application mapping. SAMOS Gereon Onnebrink, Florian Walbroel, Jonathan Klimt, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo, Stefan Schürmans, Xiaotao Chen, YwhPyng Harn
2017	—	`conf`	Extraction of recursion level parallelism for embedded multicore systems. SAMOS Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Juan Fernando Eusse
2017	—	`ch.`	MAPS: A Software Development Environment for Embedded Multicore Applications. Handbook of Hardware/Software Codesign Rainer Leupers, Miguel Angel Aguilar, Juan Fernando Eusse, Jerónimo Castrillón, Weihua Sheng
2017	Misc	`conf`	Multi-grained performance estimation for MPSoC compilers: work-in-progress. CASES Miguel Angel Aguilar, Abhishek Aggarwal, Awaid Shaheen, Rainer Leupers, Gerd Ascheid, Jerónimo Castrillón, Liam Fitzpatrick
2017	—	`conf`	Multi-level vehicle dynamics modeling and export for ADAS prototyping in a 3D driving environment. ITSC Robert Lajos Bücs, Juan Sebastian Reyes Aristizabal, Rainer Leupers, Gerd Ascheid
2017	A	`conf`	Schedule-aware loop parallelization for embedded MPSoCs by exploiting parallel slack. DATE Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias, Liam Fitzpatrick
2017	J	`jnl`	Towards Parallelism Extraction for Heterogeneous Multicore Android Devices. Int. J. Parallel Program. Miguel Angel Aguilar, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma
2017	—	`conf`	Using PEGs for Automatic Extraction of Memory Access Descriptions to Support Data-Parallel Pattern Recognition. PARMA-DITAM@HiPEAC María H. Auras-Rodríguez, Anthony Zimmermann, Gerd Ascheid, Rainer Leupers
2017	C	`conf`	VLSI implementation of LS-SVM training and classification using entropy based subset-selection. ISCAS Andreas Bytyn, Jannik Springer, Rainer Leupers, Gerd Ascheid
2016	J	`jnl`	A Scalable, Multimode SVD Precoding ASIC Based on the Cyclic Jacobi Method. IEEE Trans. Circuits Syst. I Regul. Pap. Daniel Günther, Rainer Leupers, Gerd Ascheid
2016	—	`conf`	A flexible MCMC detector ASIC. ISOCC Dominik Auras, Sebastian Birke, Tobias Piwczyk, Rainer Leupers, Gerd Ascheid
2016	J	`jnl`	An optimal allocation of memory buffers for complex multicore platforms. J. Syst. Archit. Andres Goens, Jerónimo Castrillón, Maximilian Odendahl, Rainer Leupers
2016	A*	`conf`	Automatic parallelization and accelerator offloading for embedded applications on heterogeneous MPSoCs. DAC Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Luis Gabriel Murillo
2016	—	`conf`	Automatic recognition of computational kernels for platform-dependent code optimizations. SAMOS Maria H. Rodriguez Blanco, Georg Reinke, Gerd Ascheid, Rainer Leupers
2016	—	`conf`	Black box ESL power estimation for loosely-timed TLM models. SAMOS Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Stefan Schürmans
2016	—	`conf`	Black box power estimation for digital signal processors using virtual platforms. RAPIDO@HiPEAC Gereon Onnebrink, Stefan Schürmans, Florian Walbroel, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, YwhPyng Harn
2016	—	`conf`	Concurrent memory subsystem and application optimization for ASIP design. SAMOS Juan Fernando Eusse, Francisco Fernandez, Rainer Leupers, Gerd Ascheid
2016	J	`jnl`	Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms. J. Syst. Archit. Pier Stanislao Paolucci, Andrea Biagioni, Luis Gabriel Murillo, Frédéric Rousseau, Lars Schor, Laura Tosoratto, Iuliana Bacivarov, Robert Lajos Bücs, Clément Deschamps, Ashraf El Antably, Roberto Ammendola, Nicolas Fournel, Ottorino Frezza, Rainer Leupers, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Elena Pastorelli, Devendra Rai, Davide Rossetti, Francesco Simula
2016	J	`jnl`	Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing. IEEE Trans. Very Large Scale Integr. Syst. Daniel Günther, Rainer Leupers, Gerd Ascheid
2016	J	`jnl`	Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model. ACM Trans. Embed. Comput. Syst. Stefan Schürmans, Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Xiaotao Chen
2016	—	`conf`	Low-Cost Hardware Infrastructure for Runtime Thread Level Energy Accounting. ARCS Marius Marcu, Oana Boncalo, Madalin Ghenea, Alexandru Amaricai, Jan Weinstock, Rainer Leupers, Zheng Wang, Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, Cosmin Cernazanu-Glavan, Lucian Bara, Marian Ionascu
2016	J	`jnl`	MPSoC Software Debugging on Virtual Platforms via Execution Control with Event Graphs. ACM Trans. Embed. Comput. Syst. Luis Gabriel Murillo, Robert Lajos Bücs, Rainer Leupers, Gerd Ascheid
2016	A	`conf`	Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing. DATE Daniel Günther, Tomas Henriksson, Rainer Leupers, Gerd Ascheid
2016	—	`conf`	ORVD-Trellis based MIMO detection. NEWCAS Dominik Auras, Rainer Leupers, Gerd Ascheid
2016	J	`jnl`	Parallel SystemC Simulation for ESL Design. ACM Trans. Embed. Comput. Syst. Jan Henrik Weinstock, Luis Gabriel Murillo, Rainer Leupers, Gerd Ascheid
2016	A	`conf`	SystemC-link: Parallel SystemC simulation using time-decoupled segments. DATE Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Dietmar Petras, Andreas Hoffmann
2016	A	`conf`	Technology Transfer in computing systems: The TETRACOM approach. DATE Rainer Leupers
2015	C	`conf`	A Toolflow for Parallelization of Embedded Software in Multicore DSP Platforms. SCOPES Miguel Angel Aguilar, Rainer Leupers, Gerd Ascheid, Nikolaos Kavvadias
2015	—	`conf`	A comparative investigation of device-specific mechanisms for exploiting HPC accelerators. GPGPU@PPoPP Ayman Tarakji, Lukas Börger, Rainer Leupers
2015	C	`conf`	Application-Specific Architecture Exploration Based on Processor-Agnostic Performance Estimation. SCOPES Juan Fernando Eusse, Luis Gabriel Murillo, Christopher McGirr, Rainer Leupers, Gerd Ascheid
2015	—	`conf`	Buffer Allocation Based On-Chip Memory Optimization for Many-Core Platforms. IPDPS Workshops Maximilian Odendahl, Andres Goens, Rainer Leupers, Gerd Ascheid, Tomas Henriksson
2015	J	`jnl`	CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design. ACM Trans. Reconfigurable Technol. Syst. Juan Fernando Eusse Giraldo, Christopher Williams, Rainer Leupers
2015	—	`conf`	Design and synthesis of reconfigurable control-flow structures for CGRA. ReConFig Zoltán Endre Rákossy, Axel Acosta-Aponte, Tobias G. Noll, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay
2015	—	`conf`	Deterministic event-based control of Virtual Platforms for MPSoC software debugging. SAMOS Luis Gabriel Murillo, Robert Lajos Bücs, Rainer Leupers, Gerd Ascheid
2015	—	`conf`	Direct FPGA-based power profiling for a RISC processor. I2MTC Cosmin Cernazanu-Glavan, Marius Marcu, Alexandru Amaricai, Stefan Fedeac, Madalin Ghenea, Zheng Wang, Anupam Chattopadhyay, Jan Weinstock, Rainer Leupers
2015	—	`conf`	ESL power estimation using virtual platforms with black box processor models. SAMOS Stefan Schürmans, Gereon Onnebrink, Rainer Leupers, Gerd Ascheid, Xiaotao Chen
2015	—	`conf`	Enhanced GPU Resource Utilization through Fairness-aware Task Scheduling. TrustCom/BigDataSE/ISPA (3) Ayman Tarakji, Alexander Gladis, Tarek Anwar, Rainer Leupers
2015	C	`conf`	Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture. VLSI-SoC Zoltán Endre Rákossy, Dominik Stengele, Gerd Ascheid, Rainer Leupers, Anupam Chattopadhyay
2015	—	`conf`	Extraction of Kahn Process Networks from While Loops in Embedded Software. HPCC/CSS/ICESS Miguel Angel Aguilar, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Maximilian Odendahl
2015	J	`jnl`	Flexible, Efficient Multimode MIMO Detection by Using Reconfigurable ASIP. IEEE Trans. Very Large Scale Integr. Syst. Xiaolin Chen, Andreas Minwegen, Bilal Syed Hussain, Anupam Chattopadhyay, Gerd Ascheid, Rainer Leupers
2015	C	`conf`	Modeling Exclusive Memory Access for a Time-Decoupled Parallel SystemC Simulator. SCOPES Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid
2015	A	`conf`	Multi/many-core programming: where are we standing? DATE Jerónimo Castrillón, Lothar Thiele, Lars Schor, Weihua Sheng, Ben H. H. Juurlink, Mauricio Alvarez-Mesa, Angela Pohl, Ralph Jessenberger, Victor Reyes, Rainer Leupers
2015	—	`conf`	Parallel Density-Based Stream Clustering Using a Multi-user GPU Scheduler. BDAS Ayman Tarakji, Marwan Hassani, Lyubomir Georgiev, Thomas Seidl, Rainer Leupers
2015	—	`conf`	Parallel SystemC simulation for ESL design using flexible time decoupling. SAMOS Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid
2015	—	`conf`	Parallelism extraction in embedded software for android devices. SAMOS Miguel Angel Aguilar, Juan Fernando Eusse, Projjol Ray, Rainer Leupers, Gerd Ascheid, Weihua Sheng, Prashant Sharma
2015	—	`conf`	SWAT: Assertion-based debugging of concurrency issues at system level. ASP-DAC Luis Gabriel Murillo, Robert Lajos Bücs, Daniel Hincapie, Rainer Leupers, Gerd Ascheid
2015	B	`conf`	Unified Identification of Multiple Forms of Parallelism in Embedded Applications. PACT Miguel Angel Aguilar, Rainer Leupers
2015	C	`conf`	Virtual hardware-in-the-loop co-simulation for multi-domain automotive systems via the functional mock-up interface. FDL Robert Lajos Bücs, Luis Gabriel Murillo, Ekaterina Korotcenko, Gaurav Dugge, Rainer Leupers, Gerd Ascheid, Andreas Ropers, Markus Wedler, Andreas Hoffmann
2014	—	`conf`	A Novel Class of Linear MIMO Detectors with Boosted Communications Performance: Algorithm and VLSI Architecture. ISVLSI Dominik Auras, Rainer Leupers, Gerd Ascheid
2014	—	`conf`	A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm. VLSI-SoC (Selected Papers) Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid
2014	J	`jnl`	A compiler infrastructure for embedded heterogeneous MPSoCs. Parallel Comput. Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Mark Bertsch, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid
2014	A	`conf`	A flexible ASIP architecture for connected components labeling in embedded vision applications. DATE Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid, Patrick Sudowe, Bastian Leibe, Tamon Sadasue
2014	C	`conf`	A heuristic for logical data buffer allocation in multicore platforms. IPCCC Benjamin Ries, Walter Unger, Maximilian Odendahl, Rainer Leupers
2014	—	`conf`	A novel reduced-complexity soft-input soft-output MMSE MIMO detector: Algorithm and efficient VLSI architecture. ICC Dominik Auras, Rainer Leupers, Gerd H. Ascheid
2014	A	`conf`	Automatic detection of concurrency bugs through event ordering constraints. DATE Luis Gabriel Murillo, Simon Wawroschek, Jerónimo Castrillón, Rainer Leupers, Gerd Ascheid
2014	C	`conf`	EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications Onto Many-Tile Systems. ISPA Lars Schor, Iuliana Bacivarov, Luis Gabriel Murillo, Pier Stanislao Paolucci, Frédéric Rousseau, Ashraf El Antably, Robert Buecs, Nicolas Fournel, Rainer Leupers, Devendra Rai, Lothar Thiele, Laura Tosoratto, Piero Vicini, Jan Weinstock
2014	C	`conf`	Efficient VLSI architectures for matrix inversion in soft-input soft-output MMSE MIMO detectors. ISCAS Dominik Auras, Rainer Leupers, Gerd Ascheid
2014	—	`conf`	Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systems. ISSoC Daniel Günther, Andreas Bytyn, Rainer Leupers, Gerd Ascheid
2014	C	`conf`	Improving ESL power models using switching activity information from timed functional models. SCOPES Stefan Schürmans, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Xiaotao Chen
2014	A	`conf`	Optimized buffer allocation in multicore platforms. DATE Maximilian Odendahl, Andres Goens, Rainer Leupers, Gerd Ascheid, Benjamin Ries, Berthold Vöcking, Tomas Henriksson
2014	—	`conf`	Pre-architectural performance estimation for ASIP design based on abstract processor models. ICSAMOS Juan Fernando Eusse Giraldo, Christopher Williams, Luis Gabriel Murillo, Rainer Leupers, Gerd Ascheid
2014	A	`conf`	Technology transfer towards Horizon 2020. DATE Rainer Leupers, Norbert Wehn, Marco Roodzant, Johannes Stahl, Luca Fanucci, Albert Cohen, Bernd Janson
2014	A	`conf`	Time-decoupled parallel SystemC simulation. DATE Jan Henrik Weinstock, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Laura Tosoratto
2014	C	`conf`	VLSI design of a parallel MCMC-based MIMO detector with multiplier-free Gibbs samplers. VLSI-SoC Dominik Auras, Uwe Deidersen, Rainer Leupers, Gerd Ascheid
2014	—	`conf`	VLSI implementation of linear MIMO detection with boosted communications performance: extended abstract. ACM Great Lakes Symposium on VLSI Dominik Auras, Dominik Rieth, Rainer Leupers, Gerd Ascheid
2014	J	`jnl`	legaSCi: Legacy SystemC Model Integration into Parallel Simulators. ACM Trans. Embed. Comput. Syst. Christoph Schumacher, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Laura Tosoratto, Alessandro Lonardo, Dietmar Petras, Andreas Hoffmann
2013	—	`conf`	A New Space Digital Signal Processor Design. ApplePies Massimiliano Donati, Sergio Saponara, Luca Fanucci, Walter Errico, Annamaria Colonna, Giuseppe Piscopiello, Giovanni Tuccio, Franco Bigongiari, Maximilian Odendahl, Rainer Leupers, Antonio Spada, Vincenzo Pii, Elena Cordiviola, Francesco Nuzzolo, Frederic Reiter
2013	—	`conf`	A compiler infrastructure for embedded heterogeneous MPSoCs. PMAM Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Mark Bertsch, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid
2013	J	`jnl`	Automatic Calibration of Streaming Applications for Software Mapping Exploration. IEEE Des. Test Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Rainer Leupers, Gerd Ascheid
2013	—	`conf`	CoEx: A novel profiling-based algorithm/architecture co-exploration for ASIP design. ReCoSoC Juan Fernando Eusse, Christopher Williams, Rainer Leupers
2013	A*	`conf`	Creation of ESL power models for communication architectures using automatic calibration. DAC Stefan Schürmans, Diandian Zhang, Dominik Auras, Rainer Leupers, Gerd Ascheid, Xiaotao Chen, Lun Wang
2013	—	`conf`	DSPACE hardware architecture for on-board real-time image/video processing in European space missions. Real-Time Image and Video Processing Sergio Saponara, Massimiliano Donati, Luca Fanucci, Maximilian Odendahl, Rainer Leupers, Walter Errico
2013	J	`jnl`	EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment CoRR Pier Stanislao Paolucci, Iuliana Bacivarov, Gert Goossens, Rainer Leupers, Frédéric Rousseau, Christoph Schumacher, Lothar Thiele, Piero Vicini
2013	J	`jnl`	Efficient Implementation of Application-Aware Spinlock Control in MPSoCs. Int. J. Embed. Real Time Commun. Syst. Diandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout
2013	—	`conf`	Embedded Real-Time Application Prototyping Using a Hybrid Multiprocessing Platform. HPCC/EUC Weihua Sheng, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid
2013	—	`book`	Handbook of Signal Processing Systems Handbook of Signal Processing Systems Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala
2013	J	`jnl`	MAPS: Mapping Concurrent Dataflow Applications to Heterogeneous MPSoCs. IEEE Trans. Ind. Informatics Jerónimo Castrillón, Rainer Leupers, Gerd Ascheid
2013	—	`conf`	Mapping of MIMO Receiver Algorithms onto Application-Specific Multi-Core Platforms. ISWCS Daniel Günther, Rainer Leupers, Gerd Ascheid
2013	—	`ch.`	Software Compilation Techniques for MPSoCs. Handbook of Signal Processing Systems Rainer Leupers, Weihua Sheng, Jerónimo Castrillón
2013	—	`conf`	Split-cost communication model for improved MPSoC application mapping. ISSoC Maximilian Odendahl, Jerónimo Castrillón, Vitaliy Volevach, Rainer Leupers, Gerd Ascheid
2013	—	`conf`	legaSCi: Legacy SystemC Model Integration into Parallel Systemc Simulators. IPDPS Workshops Christoph Schumacher, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Laura Tosoratto, Alessandro Lonardo, Dietmar Petras, Thorsten Grötker
2012	—	`conf`	An FPGA-accelerated testbed for hardware component development in MIMO wireless communication systems. ICSAMOS Filippo Borlenghi, Dominik Auras, Ernst Martin Witte, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2012	—	`conf`	Application-aware spinlock control using a hardware scheduler in MPSoC platforms. ISSoC Diandian Zhang, Li Lu, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout
2012	—	`conf`	Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators. HLDVT Christoph Schumacher, Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid
2012	A*	`conf`	Communication-aware mapping of KPN applications onto heterogeneous MPSoCs. DAC Jerónimo Castrillón, Andreas Tretter, Rainer Leupers, Gerd Ascheid
2012	—	`conf`	FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations. MCSoC Weihua Sheng, Artur Wiebe, Anastasia Stulova, Rainer Leupers, Bart Kienhuis, Johan Walters, Gerd Ascheid
2012	A	`conf`	Hybrid simulation for extensible processor cores. DATE Jovana Jovic, Sergey Yakoushkin, Luis Gabriel Murillo, Juan Fernando Eusse, Rainer Leupers, Gerd Ascheid
2012	—	`conf`	SCandal: SystemC Analysis for Nondeterminism Anomalies. FDL (Selected Papers) Jan Henrik Weinstock, Christoph Schumacher, Rainer Leupers, Gerd Ascheid
2012	C	`conf`	Scandal: Systemc analysis for nondeterminism anomalies. FDL Christoph Schumacher, Jan Weinstock, Rainer Leupers, Gerd Ascheid
2012	A*	`conf`	Synchronization for hybrid MPSoC full-system simulation. DAC Luis Gabriel Murillo, Juan Fernando Eusse, Jovana Jovic, Sergey Yakoushkin, Rainer Leupers, Gerd Ascheid
2012	—	`conf`	Throughput driven transformations of Synchronous Data Flows for mapping to heterogeneous MPSoCs. ICSAMOS Anastasia Stulova, Rainer Leupers, Gerd Ascheid
2012	A	`conf`	Virtual platforms: Breaking new grounds. DATE Rainer Leupers, Grant Martin, Roman Plyaskin, Andreas Herkersdorf, Frank Schirrmeister, Tim Kogel, Martin Vaupel
2011	J	`jnl`	A retargetable framework for compiler/architecture co-development. Des. Autom. Embed. Syst. Hanno Scharwächter, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2011	—	`conf`	Automatic calibration of streaming applications for software mapping exploration. SoC Weihua Sheng, Stefan Schürmans, Maximilian Odendahl, Rainer Leupers, Gerd Ascheid
2011	J	`jnl`	Checkpointing SystemC-Based Virtual Platforms. Int. J. Embed. Real Time Commun. Syst. Stefan Kraemer, Rainer Leupers, Dietmar Petras, Thomas Philipp, Andreas Hoffmann
2011	C	`conf`	Enhanced structural analysis for C code reconstruction from IR code. SCOPES Felix Engel, Rainer Leupers, Gerd Ascheid, Max Ferger, Marcel Beemster
2011	J	`jnl`	Fast graph-based instruction selection for multi-output instructions. Softw. Pract. Exp. Jonghee M. Youn, Jongwon Lee, Yunheung Paek, Jongeun Lee, Hanno Scharwächter, Rainer Leupers
2011	J	`jnl`	Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis. Int. J. Embed. Real Time Commun. Syst. Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Bart Vanthournout, Gerd Ascheid, Rainer Leupers
2011	—	`conf`	Trends in embedded software synthesis. ICSAMOS Jerónimo Castrillón, Weihua Sheng, Rainer Leupers
2011	A	`conf`	Virtual Manycore platforms: Moving towards 100+ processor cores. DATE Rainer Leupers, Lieven Eeckhout, Grant Martin, Frank Schirrmeister, Nigel P. Topham, Xiaotao Chen
2010	—	`conf`	2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures. ISVLSI Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2010	—	`conf`	2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures. ISVLSI (Selected papers) Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, Diego Melpignano, J. M. Zins, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout
2010	J	`jnl`	A Scalable VLSI Architecture for Soft-Input Soft-Output Single Tree-Search Sphere Decoding. IEEE Trans. Circuits Syst. II Express Briefs Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2010	J	`jnl`	Analytical and Simulation-based Design Space Exploration of Software Defined Radios. Int. J. Parallel Program. Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2010	J	`jnl`	Automatic Generation of Memory Interfaces for ASIPs. Int. J. Embed. Real Time Commun. Syst. David Kammler, Ernst Martin Witte, Anupam Chattopadhyay, Bastian Bauwens, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2010	A	`conf`	Cool MPSoC programming. DATE Rainer Leupers, Lothar Thiele, Xiaoning Nie, Bart Kienhuis, Matthias Weiss, Tsuyoshi Isshiki
2010	—	`book`	Handbook of Signal Processing Systems Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala
2010	—	`conf`	MPSoC programming using the MAPS compiler. ASP-DAC Rainer Leupers, Jerónimo Castrillón
2010	—	`conf`	Optimized communication architecture of MPSoCs with a hardware scheduler: A system view. SoC Diandian Zhang, Han Zhang, Jerónimo Castrillón, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Bart Vanthournout
2010	—	`ch.`	Software Compilation Techniques for MPSoCs. Handbook of Signal Processing Systems Rainer Leupers, Weihua Sheng, Jerónimo Castrillón
2010	C	`conf`	System level MPSoC design: a bright future for compiler technology? SCOPES Rainer Leupers
2010	—	`conf`	Towards Network Centric Development of Embedded Systems. ICC Stefan Schürmans, Elias Weingärtner, Torsten Kempf, Gerd Ascheid, Klaus Wehrle, Rainer Leupers
2010	A	`conf`	Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms. DATE Jerónimo Castrillón, Ricardo Velasquez, Anastasia Stulova, Weihua Sheng, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2010	Misc	`conf`	parSC: synchronous parallel systemc simulation on multi-core host architectures. CODES+ISSS Christoph Schumacher, Rainer Leupers, Dietmar Petras, Andreas Hoffmann
2009	—	`conf`	A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations. SSIRI David Kammler, Junqing Guan, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2009	—	`conf`	A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). SAMOS Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2009	J	`jnl`	A SIMD optimization framework for retargetable compilers. ACM Trans. Archit. Code Optim. Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2009	J	`jnl`	A Scalable VLSI Architecture for Soft-Input Soft-Output Depth-First Sphere Decoding CoRR Ernst Martin Witte, Filippo Borlenghi, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2009	Misc	`conf`	A Workbench for Analytical and Simulation Based Design Space Exploration of Software Defined Radios. VLSI Design Torsten Kempf, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2009	—	`conf`	A checkpoint/restore framework for systemc-based virtual platforms. SoC Stefan Kraemer, Rainer Leupers, Dietmar Petras, Thomas Philipp
2009	Misc	`conf`	A high-level virtual platform for early MPSoC software development. CODES+ISSS Jianjiang Ceng, Weihua Sheng, Jerónimo Castrillón, Anastasia Stulova, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2009	—	`conf`	Automatic generation of memory interfaces. SoC David Kammler, Bastian Bauwens, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Anupam Chattopadhyay
2009	J	`jnl`	Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves. IACR Cryptol. ePrint Arch. David Kammler, Diandian Zhang, Peter Schwabe, Hanno Scharwächter, Markus Langenberg, Dominik Auras, Gerd Ascheid, Rainer Leupers, Rudolf Mathar, Heinrich Meyr
2009	J	`jnl`	Integrated verification approach during ADL-driven processor design. Microelectron. J. Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2009	A	`conf`	Programming MPSoC platforms: Road works ahead! DATE Rainer Leupers, Andras Vajda, Marco Bekooij, Soonhoi Ha, Rainer Dömer, Achim Nohl
2009	A	`conf`	Task management in MPSoCs: An ASIP approach. ICCAD Jerónimo Castrillón, Diandian Zhang, Torsten Kempf, Bart Vanthournout, Rainer Leupers, Gerd Ascheid
2009	Misc	`conf`	TotalProf: a fast and accurate retargetable source code profiler. CODES+ISSS Lei Gao, Jia Huang, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2008	J	`jnl`	A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors. IEEE Trans. Very Large Scale Integr. Syst. Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid
2008	A	`conf`	High-level Modelling and Exploration of Coarse-grained Re-configurable Architectures. DATE Anupam Chattopadhyay, Xiaolin Chen, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2008	A*	`conf`	MAPS: an integrated framework for MPSoC application parallelization. DAC Jianjiang Ceng, Jerónimo Castrillón, Weihua Sheng, Hanno Scharwächter, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tsuyoshi Isshiki, Hiroaki Kunieda
2008	A*	`conf`	Multiprocessor performance estimation using hybrid simulation. DAC Lei Gao, Kingshuk Karuri, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2008	J	`jnl`	Power-efficient Instruction Encoding Optimization for Various Architecture Classes. J. Comput. Diandian Zhang, Anupam Chattopadhyay, David Kammler, Ernst Martin Witte, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2008	J	`jnl`	Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. ACM Trans. Embed. Comput. Syst. Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2008	A	`conf`	Retargetable Code Optimization for Predicated Execution. DATE Manuel Hohenauer, Felix Engel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gerrit Bette, Balpreet Singh
2008	J	`jnl`	SoC multiprocessor debugging and synchronisation using generic dynamic-connect debugger frontends. Int. J. Embed. Syst. Andreas Wieferink, Tim Kogel, Olaf Zerres, Rainer Leupers, Heinrich Meyr
2008	A	`conf`	System-Level Design and Application Mapping for Wireless and Multimedia MPSoC Architectures. DATE Rainer Leupers, Gerd Ascheid, Wilfried Verachtert, Tom Ashby, Arnout Vandecappelle
2008	J	`jnl`	Virtual architecture mapping: a SystemC based methodology for architectural exploration of System-on-Chips. Int. J. Embed. Syst. Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Heinrich Meyr
2007	Misc	`conf`	A code-generator generator for multi-output instructions. CODES+ISSS Hanno Scharwächter, Jonghee M. Youn, Rainer Leupers, Yunheung Paek, Gerd Ascheid, Heinrich Meyr
2007	Misc	`conf`	A fast and generic hybrid simulation approach using C virtual machine. CASES Lei Gao, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	J	`jnl`	ASIP architecture exploration for efficient IPSec encryption: A case study. ACM Trans. Embed. Comput. Syst. Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	A	`conf`	Design space exploration of partially re-configurable embedded processors. DATE Anupam Chattopadhyay, W. Ahmed, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	Misc	`conf`	HySim: a fast simulation framework for embedded software development. CODES+ISSS Stefan Kraemer, Lei Gao, Jan Weinstock, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	A	`conf`	Increasing data-bandwidth to instruction-set extensions through register clustering. ICCAD Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	A	`conf`	Interactive presentation: SoftSIMD - exploiting subword parallelism using source code transformations. DATE Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2007	—	`book`	Optimized ASIP synthesis from architecture description language models. Oliver Schliebusch, Heinrich Meyr, Rainer Leupers
2007	C	`conf`	Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. IEEE International Workshop on Rapid System Prototyping Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2006	A	`conf`	A SW performance estimation framework for early system-level-design using fine-grained instrumentation. DATE Torsten Kempf, Kingshuk Karuri, Stefan Wallentowitz, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2006	A	`conf`	A design flow for configurable embedded processors based on optimized instruction set extension synthesis. DATE Rainer Leupers, Kingshuk Karuri, Stefan Kraemer, Manas Pandey
2006	—	`conf`	ASIP design and synthesis for non linear filtering in image processing. DATE Designers' Forum Luca Fanucci, Michele Cassiano, Sergio Saponara, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2006	A	`conf`	An integrated open framework for heterogeneous MPSoC design space exploration. DATE Federico Angiolini, Jianjiang Ceng, Rainer Leupers, Federico Ferrari, Cesare Ferri, Luca Benini
2006	A	`conf`	An interprocedural code optimization technique for network processors using hardware multi-threading support. DATE Hanno Scharwächter, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2006	A	`conf`	Automatic ADL-based operand isolation for embedded processors. DATE Anupam Chattopadhyay, Benedikt Geukes, David Kammler, Ernst Martin Witte, Oliver Schliebusch, Harold Ishebabi, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2006	—	`conf`	Design and implementation of a modular and portable IEEE 754 compliant floating-point unit. DATE Designers' Forum Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia
2006	C	`conf`	Integrated Verification Approach during ADL-Driven Processor Design. IEEE International Workshop on Rapid System Prototyping Anupam Chattopadhyay, Arnab Sinha, Diandian Zhang, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2006	—	`book`	Integrated system-level modeling of network-on-chip enabled multi-processor platforms. Tim Kogel, Rainer Leupers, Heinrich Meyr
2006	—	`conf`	Memory Access Micro-Profiling for ASIP Design. DELTA Kingshuk Karuri, Christian Huben, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2006	J	`jnl`	Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. J. VLSI Signal Process. Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
2006	J	`jnl`	Offset assignment using simultaneous variable coalescing. ACM Trans. Embed. Comput. Syst. Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers
2006	Misc	`conf`	Retargetable code optimization with SIMD instructions. CODES+ISSS Manuel Hohenauer, Christoph Schumacher, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Hans van Someren
2006	Misc	`conf`	SHAPES: : a tiled scalable software hardware architecture platform for embedded systems. CODES+ISSS Pier Stanislao Paolucci, Ahmed Amine Jerraya, Rainer Leupers, Lothar Thiele, Piero Vicini
2005	A	`conf`	A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms. DATE Torsten Kempf, Malte Doerper, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tim Kogel, Bart Vanthournout
2005	—	`conf`	A framework for automated and optimized ASIP implementation supporting multiple hardware description languages. ASP-DAC Oliver Schliebusch, Anupam Chattopadhyay, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Tim Kogel
2005	A	`conf`	C Compiler Retargeting Based on Instruction Semantics Models. DATE Jianjiang Ceng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
2005	—	`ch.`	Digital Signal Processors. Handbook of Networked and Embedded Control Systems Rainer Leupers, Gerd Ascheid
2005	A*	`conf`	Fine-grained application source code profiling for ASIP design. DAC Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2005	—	`conf`	Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. ASAP Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers
2005	C	`conf`	Optimization Techniques for ADL-Driven RTL Processor Synthesis. IEEE International Workshop on Rapid System Prototyping Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr
2005	Misc	`conf`	Retargetable generation of TLM bus interfaces for MP-SoC platforms. CODES+ISSS Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Tom Michiels, Achim Nohl, Tim Kogel
2004	A	`conf`	A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. DATE Manuel Hohenauer, Hanno Scharwächter, Kingshuk Karuri, Oliver Wahlen, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Hans van Someren
2004	A	`conf`	A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform. DATE Andreas Wieferink, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun, Achim Nohl
2004	A*	`conf`	A novel approach for flexible and consistent ADL-driven ASIP design. DAC Gunnar Braun, Achim Nohl, Weihua Sheng, Jianjiang Ceng, Manuel Hohenauer, Hanno Scharwächter, Rainer Leupers, Heinrich Meyr
2004	J	`jnl`	A universal technique for fast and flexible instruction-set architecture simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr
2004	C	`conf`	ASIP Architecture Exploration for Efficient Ipsec Encryption: A Case Study. SCOPES Hanno Scharwächter, David Kammler, Andreas Wieferink, Manuel Hohenauer, Kingshuk Karuri, Jianjiang Ceng, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2004	—	`conf`	Compiler based exploration of DSP energy savings by SIMD operations. ASP-DAC Markus Lorenz, Peter Marwedel, Thorsten Dräger, Gerhard P. Fettweis, Rainer Leupers
2004	—	`conf`	Early ISS Integration into Network-on-Chip Designs. SAMOS Andreas Wieferink, Malte Doerper, Tim Kogel, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2004	—	`conf`	Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting. SAMOS Jianjiang Ceng, Weihua Sheng, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Gunnar Braun
2004	A	`conf`	RTL Processor Synthesis for Architecture Exploration and Implementation. DATE Oliver Schliebusch, Anupam Chattopadhyay, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Mario Steinert, Gunnar Braun, Achim Nohl
2004	—	`conf`	Virtual Architecture Mapping: A SystemC Based Methodology for Architectural Exploration of System-on-Chip Designs. SAMOS Tim Kogel, Malte Doerper, Torsten Kempf, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr
2003	Misc	`conf`	A modular simulation framework for architectural exploration of on-chip interconnection networks. CODES+ISSS Tim Kogel, Malte Doerper, Andreas Wieferink, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Serge Goossens
2003	C	`conf`	Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. SCOPES Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie
2003	C	`conf`	Improving Offset Assignment through Simultaneous Variable Coalescing. SCOPES Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers
2003	J	`jnl`	Instruction Scheduler Generation for Retargetable Compilation. IEEE Des. Test Comput. Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr
2003	A*	`conf`	Instruction encoding synthesis for architecture exploration using hierarchical processor models. DAC Achim Nohl, Volker Greive, Gunnar Braun, Andreas Hoffmann, Rainer Leupers, Oliver Schliebusch, Heinrich Meyr
2003	B	`conf`	Offset Assignment Showdown: Evaluation of DSP Address Code Optimization Algorithms. CC Rainer Leupers
2003	A	`conf`	Processor/Memory Co-Exploration on Multiple Abstraction Levels. DATE Gunnar Braun, Andreas Wieferink, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Achim Nohl
2002	A*	`conf`	A universal technique for fast and flexible instruction-set architecture simulation. DAC Achim Nohl, Gunnar Braun, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr, Andreas Hoffmann
2002	—	`conf`	Application specific compiler/architecture codesign: a case study. LCTES-SCOPES Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann, Rainer Leupers, Heinrich Meyr
2002	—	`book`	Architecture exploration for embedded processors with LISA. Andreas Hoffmann, Heinrich Meyr, Rainer Leupers
2002	J	`jnl`	Compiler Design Issues for Embedded Processors. IEEE Des. Test Comput. Rainer Leupers
2001	—	`conf`	C Compiler Design for an Industrial Network Processor. LCTES/OM Jens Wagner, Rainer Leupers
2001	—	`conf`	C Compiler Design for an Industrial Network Processor. OM@PLDI Jens Wagner, Rainer Leupers
2001	J	`jnl`	C compiler design for a network processor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jens Wagner, Rainer Leupers
2001	C	`conf`	Low-Energy DSP Code Generation Using a Genetic Algorithm. ICCD Markus Lorenz, Rainer Leupers, Peter Marwedel, Thorsten Dräger, Gerhard P. Fettweis
2001	—	`conf`	Optimized address assignment for DSPs with SIMD memory accesses. ASP-DAC Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel
2001	—	`book`	Retargetable compiler technology for embedded systems - tools and applications. Rainer Leupers, Peter Marwedel
2001	Misc	`conf`	Variable partitioning for dual memory bank DSPs. ICASSP Rainer Leupers, Daniel Kotte
2000	—	`conf`	Code Generation for Embedded Processors. ISSS Rainer Leupers
2000	A	`conf`	Code Selection for Media Processors with SIMD Instructions. DATE Rainer Leupers
2000	—	`book`	Code optimization techniques for embedded processors - methods, algorithms, and tools. Rainer Leupers
2000	J	`jnl`	Graph-based code selection techniques for embedded processors. ACM Trans. Design Autom. Electr. Syst. Rainer Leupers, Steven Bashford
2000	—	`conf`	Instruction Scheduling for Clustered VLIW DSPs. IEEE PACT Rainer Leupers
2000	—	`conf`	Register allocation for common subexpressions in DSP data paths. ASP-DAC Rainer Leupers
1999	Misc	`conf`	Array Index Allocation under Register Constraints in DSP Programs. VLSI Design Anupam Basu, Rainer Leupers, Peter Marwedel
1999	A*	`conf`	Constraint Driven Code Selection for Fixed-Point DSPs. DAC Steven Bashford, Rainer Leupers
1999	A	`conf`	Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors. DATE Rainer Leupers
1999	A	`conf`	Function inlining under code size constraints for embedded processors. ICCAD Rainer Leupers, Peter Marwedel
1999	—	`conf`	Generation of Interpretive and Compiled Instruction Set Simulators. ASP-DAC Rainer Leupers, Johann Elste, Birger Landwehr
1999	J	`jnl`	Phase-Coupled Mapping of Data Flow Graphs to Irregular Data Paths. Des. Autom. Embed. Syst. Steven Bashford, Rainer Leupers
1998	—	`conf`	A Uniform Optimization Technique for Offset Assignment Problems. ISSS Rainer Leupers, Fabian David
1998	—	`conf`	HDL-Based Modeling of Embedded Processor Behavior for Retargetable Compilation. ISSS Rainer Leupers
1998	—	`conf`	Optimized Array Index Computation in DSP Programs. ASP-DAC Rainer Leupers, Anupam Basu, Peter Marwedel
1998	A	`conf`	Register-Constrained Address Computation in DSP Programs. DATE Anupam Basu, Rainer Leupers, Peter Marwedel
1998	J	`jnl`	Retargetable Code Generation Based on Structural Processor Description. Des. Autom. Embed. Syst. Rainer Leupers, Peter Marwedel
1997	—	`book`	Retargetable code generation for digital signal processors. Rainer Leupers
1997	—	`conf`	Retargetable generation of code selectors from HDL processor models. ED&TC Rainer Leupers, Peter Marwedel
1997	J	`jnl`	Time-constrained code compaction for DSPs. IEEE Trans. Very Large Scale Integr. Syst. Rainer Leupers, Peter Marwedel
1996	A	`conf`	Algorithms for address assignment in DSP code generation. ICCAD Rainer Leupers, Peter Marwedel
1996	—	`conf`	Instruction selection for embedded DSPs with complex instructions. EURO-DAC Rainer Leupers, Peter Marwedel
1996	Misc	`conf`	Instruction-Set Modeling for ASIP Code Generation. VLSI Design Rainer Leupers, Peter Marwedel
1995	—	`conf`	A BDD-based frontend for retargetable compilers. ED&TC Rainer Leupers, Peter Marwedel
1995	—	`conf`	Time-constrained code compaction for DSPs. ISSS Rainer Leupers, Peter Marwedel
1995	B	`conf`	Using compilers for heterogeneous system design. PACT Rainer Leupers, Peter Marwedel
1994	—	`conf`	Instruction set extraction from programmable structures. EURO-DAC Peter Marwedel, Rainer Leupers
1994	—	`conf`	Microcode Generation for Flexible Parallel Target Architectures. IFIP PACT Rainer Leupers, Wolfgang Schenk, Peter Marwedel
1994	—	`conf`	Retargetable assembly code generation by bootstrapping. HLSS Rainer Leupers, Wolfgang Schenk, Peter Marwedel
1993	A*	`conf`	Resistance Extraction using a Routing Algorithm. DAC Lorenz Ladage, Rainer Leupers