Rainer Kress - RankMe

27 papers A* 1A 4B 8Misc 1Journal 2Unranked 10

Year	Rank	Type	Title / Venue / Authors
2014	A	`conf`	Panel: The world is going... analog & mixed-signal! What about EDA? DATE Marco Casale-Rossi, Pietro Palella, Mario Anton, Ori Galzur, Robert Hum, Rainer Kress, Paul Lo
2012	A	`conf`	Panel: What is EDA doing for trailing edge technologies? DATE Marco Casale-Rossi, Pierluigi Rolandi, Andreas Bruening, Antun Domic, Rainer Kress, Joseph Sawicki, Christian Sebeke
2000	B	`conf`	FPGA-Based Prototyping for Product Definition. FPL Rainer Kress, Andreas Pyttel, Alexander Sedlmeier
2000	—	`conf`	Role-Centered Conceptual Modeling in System Design. MBMV Michael Mrva, Rainer Kress
1999	A	`conf`	Codesign of Embedded Systems Based on Java and Reconfigurable Hardware Components. DATE Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
1999	B	`conf`	Debugging Application-Specific Programmable Products. FPL Rainer Kress, Andreas Pyttel
1999	A*	`conf`	Java Driven Codesign and Prototyping of Networked Embedded Systems. DAC Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
1998	A	`conf`	A Scalable Architecture for Multi-threaded JAVA Applications. DATE Michael Mrva, Klaus Buchenrieder, Rainer Kress
1998	—	`conf`	A hardware/software prototyping environment for dynamically reconfigurable embedded systems. CODES Josef Fleischmann, Klaus Buchenrieder, Rainer Kress
1998	B	`conf`	High-Level Synthesis for Dynamically Reconfigurable Hardware/Software Systems. FPL Rainer Kress, Andreas Pyttel
1997	B	`conf`	An operating system for custom computing machines based on the Xputer paradigm. FPL Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger
1996	—	`conf`	A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
1996	—	`conf`	A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger
1996	—	`—`	A fast reconfigurable ALU for Xputers. Rainer Kress
1996	—	`conf`	An Embedded Accelerator for Real-Time Image Processing. RTS Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1996	Misc	`conf`	CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
1996	B	`conf`	Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. FPL Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1996	J	`jnl`	High-performance computing using a reconfigurable accelerator. Concurr. Pract. Exp. Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig
1996	—	`conf`	Two-Level Hardware/Software Partitioning Using CoDe-X. ECBS Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1996	—	`conf`	Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. CODES Reiner W. Hartenstein, Jürgen Becker, Rainer Kress
1995	—	`conf`	A Parallelizing Compilation Method for the Map-oriented Machine. ASAP Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt
1995	—	`conf`	A datapath synthesis system for the reconfigurable datapath architecture. ASP-DAC Reiner W. Hartenstein, Rainer Kress
1994	B	`conf`	A New FPGA Architecture for Word-Oriented Datapaths. FPL Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
1994	—	`conf`	A dynamically reconfigurable wavefront array architecture for evaluation of expressions. ASAP Reiner W. Hartenstein, Rainer Kress, Helmut Reinig
1994	B	`conf`	Data-Procedural Languages for FPL-based Machines. FPL Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt
1993	J	`jnl`	CMOS interconnect modelling for timing analysis. Microprocess. Microprogramming Rainer Kress, Elmar U. K. Melcher, Reiner W. Hartenstein, Michel Dana
1992	B	`conf`	Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. FPL Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt