Rainer G. Spallek

61 papers A 3B 16C 4Misc 1Journal 2Unranked 34

Year	Rank	Type	Title / Venue / Authors
2020	—	`conf`	Possibilities and Challenges for Reconfigurable Hardware and Cloud Architectures in Data-Intensive Scientific Applications. SDS Mohammed Bawatna, Oliver Knodel, Rainer G. Spallek
2020	—	`conf`	Real-Time Data Compression System for Data-Intensive Scientific Applications Using FPGA Architecture. CSOC (3) Mohammed Bawatna, Oliver Knodel, Rainer G. Spallek
2019	—	`conf`	Research and Implementation of Efficient Parallel Processing of Big Data at TELBE User Facility. SPECTS Mohammed Bawatna, Bertram Green, Sergey Kovalev, Jan-Christoph Deinert, Oliver Knodel, Rainer G. Spallek
2019	—	`conf`	Research and implementation of efficient parallel processing of big data at TELBE user facility. SummerSim Mohammed Bawatna, Bertram Green, Sergey Kovalev, Jan-Christoph Deinert, Oliver Knodel, Rainer G. Spallek
2017	—	`conf`	A New Level of Trusted Cloud Computing - Virtualized Reconfigurable Resources in a Security-First Architecture. GI-Jahrestagung Paul R. Genßler, Oliver Knodel, Rainer G. Spallek
2017	—	`conf`	First Workshop on Hardware Defined Programming - HDP. GI-Jahrestagung Oliver Knodel, Steffen Köhler, Marko Rößler, Rainer G. Spallek
2017	—	`conf`	Modellierung anwendungsspezifischer Hardware und deren Einbettung in die DBT-basierte Prozessor-Verhaltenssimulation. GI-Jahrestagung Steffen Köhler, Rainer G. Spallek
2016	J	`jnl`	Migration of long-running Tasks between Reconfigurable Resources using Virtualization. SIGARCH Comput. Archit. News Oliver Knodel, Paul R. Genssler, Rainer G. Spallek
2016	B	`conf`	RC3E: Reconfigurable Accelerators in Data Centres and Their Provision by Adapted Service Models. CLOUD Oliver Knodel, Patrick Lehmann, Rainer G. Spallek
2016	—	`conf`	The portable open-source IP core and utility library PoC. ReConFig Thomas B. Preußer, Martin Zabel, Patrick Lehmann, Rainer G. Spallek
2015	C	`conf`	Computing Framework for Dynamic Integration of Reconfigurable Resources in a Cloud. DSD Oliver Knodel, Rainer G. Spallek
2015	—	`conf`	Kompression von Tracedaten auf Bitebene basierend auf einem LZ77-Wörterbuchansatz. GI-Jahrestagung Kai-Uwe Irrgang, Thomas B. Preußer, Rainer G. Spallek
2015	J	`jnl`	RC3E: Provision and Management of Reconfigurable Hardware Accelerators in a Cloud Environment. CoRR Oliver Knodel, Rainer G. Spallek
2014	B	`conf`	Educating hardware design - From primary school children to postgraduate engineers. FPL Oliver Knodel, Martin Zabel, Patrick Lehmann, Rainer G. Spallek
2014	—	`conf`	PoC-align: An open-source alignment accelerator using FPGAs. ReConFig Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek
2014	B	`conf`	Ready PCIe data streaming solutions for FPGAs. FPL Thomas B. Preußer, Rainer G. Spallek
2013	B	`conf`	Integration of a Highly Scalable, Multi-FPGA-Based Hardware Accelerator in Common Cluster Infrastructures. ICPP Oliver Knodel, Andy Georgi, Patrick Lehmann, Wolfgang E. Nagel, Rainer G. Spallek
2013	B	`conf`	Integration of a multi-FPGA system in a common cluster environment. FPL Oliver Knodel, Rainer G. Spallek
2013	B	`conf`	Superblock compilation and other optimization techniques for a Java-based DPT machine emulator. VEE Marco Kaufmann, Rainer G. Spallek
2013	B	`conf`	Weasel: A platform-independent streaming-optimized SATA controller. FPL Patrick Lehmann, Thomas Frank, Oliver Knodel, Steffen Köhler, Thomas B. Preußer, Rainer G. Spallek
2012	—	`conf`	Comparison of Trace-Port-Designs for On-Chip-Instruction-Trace. IEEE GSC Kai-Uwe Irrgang, Rainer G. Spallek
2012	—	`conf`	Increasing the efficiency of an embedded multi-core bytecode processor using an object cache. JTRES Martin Zabel, Thomas B. Preußer, Rainer G. Spallek
2012	Misc	`conf`	Short-Read Mapping by a Systolic Custom FPGA Computation. FCCM Thomas B. Preußer, Oliver Knodel, Rainer G. Spallek
2011	C	`conf`	Accelerating Computations on FPGA Carry Chains by Operand Compaction. IEEE Symposium on Computer Arithmetic Thomas B. Preußer, Martin Zabel, Rainer G. Spallek
2011	—	`conf`	Next-generation massively parallel short-read mapping on FPGAs. ASAP Oliver Knodel, Thomas B. Preußer, Rainer G. Spallek
2011	—	`conf`	The Java Virtual Machine in retargetable, high-performance instruction set simulation. PPPJ Marco Kaufmann, Matthias Häsing, Thomas Preußer, Rainer G. Spallek
2010	—	`conf`	An Embedded GC Module with Support for Multiple Mutators and Weak References. ARCS Thomas B. Preußer, Peter Reichel, Rainer G. Spallek
2010	—	`conf`	Application requirements and efficiency of embedded Java bytecode multi-cores. JTRES Martin Zabel, Rainer G. Spallek
2010	B	`conf`	Enhancing FPGA Device Capabilities by the Automatic Logic Mapping to Additive Carry Chains. FPL Thomas B. Preußer, Rainer G. Spallek
2010	—	`conf`	Solving Sudokus through an incidence matrix on an FPGA. FPT Michael Dittrich, Thomas B. Preußer, Rainer G. Spallek
2009	A	`conf`	Generating the trace qualification configuration for MCDS from a high level language. DATE Jens Braunes, Rainer G. Spallek
2009	—	`conf`	High-Level Architecture Modelling Assisting the Processor Platform Development, Debugging and Simulation. MBMV Martin Zabel, Thomas B. Preußer, Rainer G. Spallek
2009	B	`conf`	Mapping basic prefix computations to fast carry-chain structures. FPL Thomas B. Preußer, Rainer G. Spallek
2008	—	`ed.`	Architecture of Computing Systems - ARCS 2008, 21st International Conference, Dresden, Germany, February 25-28, 2008, Proceedings ARCS Uwe Brinkschulte, Theo Ungerer, Christian Hochberger, Rainer G. Spallek
2008	—	`conf`	Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study. ARC Steffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek
2008	A	`conf`	Java-Programmed Bootloading in Spite of Load-Time Code Patching on a Minimal Embedded Bytecode Processor. ESA Thomas Preußer, Rainer G. Spallek
2007	—	`conf`	Bump-pointer method caching for embedded Java processors. JTRES Thomas Preußer, Martin Zabel, Rainer G. Spallek
2007	—	`conf`	Enabling constant-time interface method dispatch in embedded Java processors. JTRES Thomas Preußer, Martin Zabel, Rainer G. Spallek
2007	C	`conf`	Implementation of Architecture Concepts for Hardware Agent Systems. CIT Jörg Schneider, Marcel Naggatz, Rainer G. Spallek
2007	C	`conf`	Secure, Real-Time and Multi-Threaded General-Purpose Embedded Java Microarchitecture. DSD Martin Zabel, Thomas B. Preußer, Peter Reichel, Rainer G. Spallek
2006	—	`conf`	A Compiler-Oriented Architecture Description for Reconfigurable Systems. ARC Jens Braunes, Rainer G. Spallek
2006	—	`conf`	Analysis of a Fully-Scalable Digital Fractional Clock Divider. ASAP Thomas B. Preußer, Rainer G. Spallek
2006	—	`conf`	Prototyping and Application Development Framework for Dynamically Reconfigurable DSP Architectures. ARCS Workshops Steffen Köhler, Martin Zimmerling, Martin Zabel, Rainer G. Spallek
2005	—	`conf`	Design space exploration of coarse-grain reconfigurable DSPs. ReConFig Martin Zabel, Steffen Köhler, Martin Zimmerling, Thomas B. Preußer, Rainer G. Spallek
2005	—	`conf`	Ein Zwischenformat-Profiler für das RECAST-Framework. ARCS Workshops Jens Braunes, Steffen Köhler, Annett Königsmann, Rainer G. Spallek
2004	B	`conf`	Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. FPL Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek
2004	—	`conf`	RECAST - Design Space Exploration for Dynamic Reconfigurable Embedded Computing. ESA/VLSI Thomas Preußer, Steffen Köhler, Rainer G. Spallek
2004	—	`conf`	RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures. ARCS Jens Braunes, Steffen Köhler, Rainer G. Spallek
2003	B	`conf`	Architecture Template and Design Flow to Support Applications Parallelism on Reconfigurable Platforms. FPL Sergej Sawitzki, Rainer G. Spallek
2002	B	`conf`	A Reconfigurable System-on-Chip-Based Fast EDM Process Monitor. FPL Sebastian Friebe, Steffen Köhler, Rainer G. Spallek, Henrik Juhr, Klaus Künanz
2002	A	`conf`	Improving Code Efficiency for Reconfigurable VLIW Processors. IPDPS Steffen Köhler, Jens Braunes, Sergej Sawitzki, Rainer G. Spallek
2001	B	`conf`	Prototyping Framework for Reconfigurable Processors. FPL Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek
2000	—	`conf`	Experimenteller Vergleich verschiedener Entwurfsmethoden für FPGA-basierte Entwurfsabläufe. MBMV Sergej Sawitzki, Steffen Köhler, Rainer G. Spallek, Jörg Schneider, S. Rülke
2000	—	`conf`	Formal Verification for Microprocessors with Extendable Instruction Set. ASAP Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube
2000	B	`conf`	Formal Verification of a Reconfigurable Microprocessor. FPL Sergej Sawitzki, Jens Schönherr, Rainer G. Spallek, Bernd Straube
1999	B	`conf`	A Concept for an Evaluation Framework for Reconfigurable Systems. FPL Sergej Sawitzki, Rainer G. Spallek
1999	—	`conf`	Digital Signal Processing with General Purpose Microprocessors, DSP and Rcinfigurable Logic. IPPS/SPDP Workshops Steffen Köhler, Sergej Sawitzki, Achim Gratz, Rainer G. Spallek
1998	—	`conf`	Common Logging Interface - Ein System zum Sammeln und Verarbeiten von Debugnachrichten in verteilten Umgebungen. Java-Informations-Tage Raimar Falke, Michael Peter, Achim Gratz, Rainer G. Spallek
1998	B	`conf`	Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays. FPL Sergej Sawitzki, Achim Gratz, Rainer G. Spallek
1997	—	`conf`	A RISC Processor with Extended Forwarding. ARCS Gert Markwardt, Günter Kemnitz, Rainer G. Spallek
1997	—	`conf`	Bewertung von modernen Rechnerarchitekturen hinsichtlich numerischer Simulationen auf heterogenen Plattformen. MMB (Kurzbeiträge) Achim Gratz, Rainer G. Spallek