Raimund Ubar - RankMe

188 papers A 8B 11C 49Misc 5Journal 35Unranked 78

Year	Rank	Type	Title / Venue / Authors
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2024	—	`book`	Structural Decision Diagrams in Digital Test - Theory and Applications Raimund Ubar, Jaan Raik, Maksim Jenihhin, Artur Jutman
2022	—	`conf`	High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. ISVLSI Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar
2021	C	`conf`	Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor Modules. DSD Maksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar
2021	J	`jnl`	Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. CoRR Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer
2020	J	`jnl`	Calculation of probabilistic testability measures for digital circuits with Structurally Synthesized BDDs. Microprocess. Microsystems Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2020	J	`jnl`	High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors. J. Electron. Test. Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2020	C	`conf`	Implementation-Independent Functional Test for Transition Delay Faults in Microprocessors. DSD Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2020	J	`jnl`	New categories of Safe Faults in a processor-based Embedded System. CoRR Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar
2020	C	`conf`	Representing Gate-Level SET Faults by Multiple SEU Faults at RTL. IOLTS Ahmet Cagri Bagbaba, Maksim Jenihhin, Raimund Ubar, Christian Sauer
2019	C	`conf`	Application Specific True Critical Paths Identification in Sequential Circuits. IOLTS Lembit Jürimägi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Adeboye Stephen Oyeniran
2019	—	`conf`	Equivalent Transformations of Structurally Synthesized BDDs and Applications. MECO Lembit Jürimägi, Raimund Ubar, Vladimir Viies
2019	B	`conf`	High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors. ETS Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
2019	J	`jnl`	High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors. CoRR Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
2019	—	`conf`	High-Level Functional Test Generation for Microprocessor Modules. MIXDES Adeboye Stephen Oyeniran, Raimund Ubar
2019	C	`conf`	Implementation-Independent Functional Test Generation for MSC Microprocessors. VLSI-SoC Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2019	—	`conf`	Mixed-level identification of fault redundancy in microprocessors. LATS Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
2019	J	`jnl`	Mixed-level identification of fault redundancy in microprocessors. CoRR Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Cemil Cem Gürsoy, Jaan Raik
2019	C	`conf`	New categories of Safe Faults in a processor-based Embedded System. DDECS Cemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar
2019	—	`conf`	On Test Generation for Microprocessors for Extended Class of Functional Faults. VLSI-SoC (Selected Papers) Adeboye Stephen Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
2019	C	`conf`	True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital Circuits. DSD Raimund Ubar, Lembit Jürimägi, Adeniyi Olanrewaju Adekoya, Maksim Jenihhin
2018	—	`conf`	Combined pseudo-exhaustive and deterministic testing of array multipliers. AQTR Adeboye Stephen Oyeniran, Siavoosh Payandeh Azad, Raimund Ubar
2018	J	`jnl`	Fast identification of true critical paths in sequential circuits. Microelectron. Reliab. Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Lembit Jürimägi
2018	—	`conf`	Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. PATMOS Lembit Jurimagi, Raimund Ubar, Maksim Jenihhin, Jaan Raik, Sergei Devadze, Sergei Kostin
2018	—	`conf`	Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. MIXDES Jaak Kousaar, Raimund Ubar, Sergei Kostin, Sergei Devadze, Jaan Raik
2018	C	`conf`	Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation. ISCAS Adeboye Stephen Oyeniran, Siavoosh Payandeh Azad, Raimund Ubar
2018	C	`conf`	Replication-Based Deterministic Testing of 2-Dimensional Arrays with Highly Interrelated Cells. DDECS Siavoosh Payandeh Azad, Adeboye Stephen Oyeniran, Raimund Ubar
2018	—	`conf`	Timing-critical path analysis with structurally synthesized BDDs. MECO Raimund Ubar, Lembit Jurimagi, Maksim Jenihhin, Jaan Raik, Niyi-Leigh Olugbenga, Vladimir Viies
2017	C	`conf`	A scalable technique to identify true critical paths in sequential circuits. DDECS Raimund Ubar, Sergei Kostin, Maksim Jenihhin, Jaan Raik
2017	—	`conf`	Automated software-based self-test generation for microprocessors. MIXDES Artjom Jasnetski, Raimund Ubar, Anton Tsertov
2017	C	`conf`	From online fault detection to fault management in Network-on-Chips: A ground-up approach. DDECS Siavoosh Payandeh Azad, Behrad Niazmand, Karl Janson, Nevin George, Stephen Adeboye Oyeniran, Tsotne Putkaradze, Apneet Kaur, Jaan Raik, Gert Jervan, Raimund Ubar, Thomas Hollstein
2017	—	`conf`	High-level test data generation for software-based self-test in microprocessors. MECO Adeboye Stephen Oyeniran, Artjom Jasnetski, Anton Tsertov, Raimund Ubar
2017	—	`conf`	High-level test generation for processing elements in many-core systems. ReCoSoC Stephen Adeboye Oyeniran, Raimund Ubar, Siavoosh Payandeh Azad, Jaan Raik
2017	J	`jnl`	Modeling and simulation of circuits with shared structurally synthesized BDDs. Microprocess. Microsystems Raimund Ubar, Lembit Jürimägi, Jaan Raik, Vladimir Viies
2016	—	`conf`	A novel random approach to diagnostic test generation. NORCAS Emmanuel Ovie Osimiry, Raimund Ubar, Sergei Kostin, Jaan Raik
2016	—	`conf`	A tool set for teaching design-for-testability of digital circuits. EWME Sergei Kostin, Elmet Orasson, Raimund Ubar
2016	—	`conf`	Gate-level modelling of NBTI-induced delays under process variations. LATS Thiago Copetti, Guilherme Medeiros Machado, Leticia Bolzani Poehls, Fabian Vargas, Sergei Kostin, Maksim Jenihhin, Jaan Raik, Raimund Ubar
2016	C	`conf`	High-level modeling and testing of multiple control faults in digital systems. DDECS Artjom Jasnetski, Stephen Adeboye Oyeniran, Anton Tsertov, Mario Schölzel, Raimund Ubar
2016	J	`jnl`	Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits. J. Electron. Test. Maksim Jenihhin, Giovanni Squillero, Thiago Santos Copetti, Valentin Tihhomirov, Sergei Kostin, Marco Gaudesi, Fabian Vargas, Jaan Raik, Matteo Sonza Reorda, Leticia Bolzani Poehls, Raimund Ubar, Guilherme Cardoso Medeiros
2016	—	`conf`	Multiple control fault testing in digital systems with high-level decision diagrams. AQTR Raimund Ubar, Stephen Adeboye Oyeniran
2016	—	`conf`	On automatic software-based self-test program generation based on high-level decision diagrams. LATS Artjom Jasnetski, Raimund Ubar, Anton Tsertov
2016	—	`conf`	Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs. ATS Francesco Pellerey, Maksim Jenihhin, Giovanni Squillero, Jaan Raik, Matteo Sonza Reorda, Valentin Tihhomirov, Raimund Ubar
2015	C	`conf`	Combinational fault simulation in sequential circuits. ISCAS Raimund Ubar, Jaak Kousaar, Maksim Gorev, Sergei Devadze
2015	—	`conf`	Complex delay fault reasoning with sequential 7-valued algebra. LATS Jaak Kousaar, Raimund Ubar, Igor Aleksejev
2015	C	`conf`	Double Phase Fault Collapsing with Linear Complexity in Digital Circuits. DSD Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Galina Josifovska, Stephen Adeboye Oyeniran
2015	—	`conf`	Fault Collapsing in Digital Circuits Using Fast Fault Dominance and Equivalence Analysis with SSBDDs. VLSI-SoC (Selected Papers) Raimund Ubar, Lembit Jürimägi, Elmet Orasson, Jaan Raik
2015	A	`conf`	Fault simulation with parallel exact critical path tracing in multiple core environment. DATE Maksim Gorev, Raimund Ubar, Sergei Devadze
2015	J	`jnl`	Functional self-test of high-performance pipe-lined signal processing architectures. Microprocess. Microsystems Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
2015	—	`conf`	Multiple fault testing in systems-on-chip with high-level decision diagrams. IDT Raimund Ubar, Stephen Adeboye Oyeniran, Mario Schölzel, Heinrich Theodor Vierhaus
2015	C	`conf`	New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams. DDECS Artjom Jasnetski, Jaan Raik, Anton Tsertov, Raimund Ubar
2015	C	`conf`	SPICE-Inspired Fast Gate-Level Computation of NBTI-induced Delays in Nanoscale Logic. DDECS Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Thiago Copetti, Fabian Vargas, Letícia Maria Bolzani Pöhls
2015	C	`conf`	Scalable algorithm for structural fault collapsing in digital circuits. VLSI-SoC Raimund Ubar, Lembit Jurimagi, Elmet Orasson, Jaan Raik
2015	—	`conf`	Shared Structurally Synthesized BDDs for speeding-up parallel pattern simulation in digital circuits. NORCAS Raimund Ubar, Lembit Jurimagi, Jaan Raik
2015	J	`jnl`	Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. Microprocess. Microsystems Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik
2014	—	`conf`	Advanced technical education in the age of cyber physical systems. EWME Heinrich Theodor Vierhaus, Mario Schölzel, Jaan Raik, Raimund Ubar
2014	J	`jnl`	Automated Design Error Localization in RTL Designs. IEEE Des. Test Maksim Jenihhin, Anton Tsepurov, Valentin Tihhomirov, Jaan Raik, Hanno Hantson, Raimund Ubar, Gunter Bartsch, Jorge Hernán Meza Escobar, Heinz-Dietrich Wuttke
2014	C	`conf`	Critical Path Tracing Based Simulation of Transition Delay Faults. DSD Jaak Kousaar, Raimund Ubar, Sergei Devadze, Jaan Raik
2014	B	`conf`	Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation. EvoApplications Marco Gaudesi, Maksim Jenihhin, Jaan Raik, Ernesto Sánchez, Giovanni Squillero, Valentin Tihhomirov, Raimund Ubar
2014	—	`conf`	Hierarchical identification of NBTI-critical gates in nanoscale logic. LATW Sergei Kostin, Jaan Raik, Raimund Ubar, Maksim Jenihhin, Fabian Vargas, Letícia Maria Bolzani Poehls, Thiago Santos Copetti
2014	—	`conf`	Laboratory framework TEAM for investigating the dependability issues of microprocessor systems. EWME Artjom Jasnetski, Raimund Ubar, Anton Tsertov, Helena Kruus
2014	B	`conf`	Logic simulation and fault collapsing with shared structurally synthesized bdds. ETS Dmitri Mironov, Raimund Ubar, Jaan Raik
2014	C	`conf`	Lower bounds of the size of Shared Structurally Synthesized BDDs. DDECS Raimund Ubar, Dmitri Mironov
2014	—	`conf`	Modeling sequential circuits with shared structurally synthesized BDDs. IDT Raimund Ubar, Mihhail Marenkov, Dmitri Mironov, Vladimir Viies
2014	—	`conf`	Software-based self-test generation for microprocessors with high-level decision diagrams. LATW Raimund Ubar, Anton Tsertov, Artjom Jasnetski, Marina Brik
2013	J	`jnl`	Accurate Dialysis Dose Evaluation and Extrapolation Algorithms During Online Optical Dialysis Monitoring. IEEE Trans. Biomed. Eng. Ivo Fridolin, Deniss Karai, Sergei Kostin, Raimund Ubar
2013	—	`conf`	Assessment of diagnostic test for automated bug localization. LATW Valentin Tihhomirov, Anton Tsepurov, Maksim Jenihhin, Jaan Raik, Raimund Ubar
2013	—	`conf`	At-speed self-testing of high-performance pipe-lined processing architectures. NORCHIP Maksim Gorev, Raimund Ubar, Peeter Ellervee, Sergei Devadze, Jaan Raik, Mart Min
2013	J	`jnl`	Automated design error debug using high-level decision diagrams and mutation operators. Microprocess. Microsystems Jaan Raik, Urmas Repinski, Anton Chepurov, Hanno Hantson, Raimund Ubar, Maksim Jenihhin
2013	—	`conf`	Diagnostic modeling of digital systems with low- and high-level decision diagrams. LATW Raimund Ubar
2013	C	`conf`	Identifying NBTI-Critical Paths in Nanoscale Logic. DSD Raimund Ubar, Fabian Vargas, Maksim Jenihhin, Jaan Raik, Sergei Kostin, Letícia Maria Bolzani Poehls
2013	—	`conf`	Synthesis of multiple fault oriented test groups from single fault test sets. DTIS Raimund Ubar, Sergei Kostin, Jaan Raik
2012	—	`conf`	About robustness of test patterns regarding multiple faults. LATW Raimund Ubar, Sergei Kostin, Jaan Raik
2012	—	`conf`	Automated correction of design errors by edge redirection on High-Level Decision Diagrams. ISQED Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik
2012	B	`conf`	Combining dynamic slicing and mutation operators for ESL correction. ETS Urmas Repinski, Hanno Hantson, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Giuseppe Di Guglielmo, Graziano Pravadelli, Franco Fummi
2012	—	`conf`	Diagnosis and correction of multiple design errors using critical path tracing and mutation analysis. LATW Hanno Hantson, Urmas Repinski, Jaan Raik, Maksim Jenihhin, Raimund Ubar
2012	—	`conf`	Functional Built-In Self-Test for processor cores in SoC. NORCHIP Raimund Ubar, Viljar Indus, Oliver Kalmend, Teet Evartson, Elmet Orasson
2012	C	`conf`	How to Prove that a Circuit is Fault-Free? DSD Raimund Ubar, Sergei Kostin, Jaan Raik
2012	C	`ed.`	IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2012, Tallinn, Estonia, April 18-20, 2012 DDECS Jaan Raik, Viera Stopjaková, Heinrich Theodor Vierhaus, Witold A. Pleskacz, Raimund Ubar, Helena Kruus, Maksim Jenihhin
2012	J	`jnl`	Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints. J. Electron. Test. Taavi Viilukas, Anton Karputkin, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Hideo Fujiwara
2012	C	`conf`	Multiple stuck-at-fault detection theorem. DDECS Raimund Ubar, Sergei Kostin, Jaan Raik
2012	J	`jnl`	On the Reuse of TLM Mutation Analysis at RTL. J. Electron. Test. Valerio Guarnieri, Giuseppe Di Guglielmo, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar
2011	—	`conf`	Automated test bench generation for high-level synthesis flow ABELITE. EWDTS Taavi Viilukas, Maksim Jenihhin, Jaan Raik, Raimund Ubar, Samary Baranov
2011	—	`conf`	Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. Asian Test Symposium Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
2011	B	`conf`	Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. ETS Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara
2011	C	`conf`	Defect-oriented module-level fault diagnosis in digital circuits. DDECS Sergei Kostin, Raimund Ubar, Jaan Raik
2011	J	`jnl`	Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits. Scalable Comput. Pract. Exp. Eero Ivask, Sergei Devadze, Raimund Ubar
2011	—	`conf`	Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations. DFT Uljana Reinsalu, Jaan Raik, Raimund Ubar, Peeter Ellervee
2011	—	`conf`	Interactive presentation abstract: Automated correction of design errors by edge redirection on high-level decision diagrams. HLDVT Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik
2011	—	`conf`	Mutation analysis for SystemC designs at TLM. LATW Valerio Guarnieri, Nicola Bombieri, Graziano Pravadelli, Franco Fummi, Hanno Hantson, Jaan Raik, Maksim Jenihhin, Raimund Ubar
2011	C	`conf`	Probabilistic equivalence checking based on high-level decision diagrams. DDECS Anton Karputkin, Raimund Ubar, Mati Tombak, Jaan Raik
2011	C	`conf`	SoC and Board Modeling for Processor-Centric Board Testing. DSD Anton Tsertov, Raimund Ubar, Artur Jutman, Sergei Devadze
2010	—	`conf`	An approach for PSL assertion coverage analysis with high-level decision diagrams. EWDTS Maksim Jenihhin, Jaan Raik, Raimund Ubar, Tatjana Shchenova
2010	—	`conf`	Collaborative Distributed Computing in the Field of Digital Electronics Testing. BASYS Eero Ivask, Sergei Devadze, Raimund Ubar
2010	Misc	`conf`	Collaborative Distributed Fault Simulation for Digital Electronic Circuits. IDC Eero Ivask, Sergei Devadze, Raimund Ubar
2010	C	`conf`	Constraint-based test pattern generation at the Register-Transfer Level. DDECS Taavi Viilukas, Jaan Raik, Maksim Jenihhin, Raimund Ubar, Anna Krivenko
2010	J	`jnl`	Evolutionary Approach to Test Generation for Functional BIST CoRR Yuriy A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, Raimund Ubar, Jaan Raik
2010	—	`conf`	Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. DELTA Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2010	C	`conf`	Fault collapsing with linear complexity in digital circuits. ISCAS Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman
2010	—	`conf`	Mutation analysis with high-level decision diagrams. LATW Hanno Hantson, Jaan Raik, Maksim Jenihhin, Anton Chepurov, Raimund Ubar, Giuseppe Di Guglielmo, Franco Fummi
2010	A	`conf`	Parallel X-fault simulation with critical path tracing technique. DATE Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2010	C	`conf`	Remote and Virtual Laboratories in Problem-Based Learning Scenarios. ISM Heinz-Dietrich Wuttke, Raimund Ubar, Karsten Henke
2010	—	`conf`	Structural fault collapsing by superposition of BDDs for test generation in digital circuits. ISQED Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman
2010	C	`conf`	Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2009	C	`conf`	Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. DSD Raimund Ubar, Sergei Kostin, Jaan Raik
2009	J	`jnl`	Design-for-testability-based external test and diagnosis of mesh-like network-on-a-chips. IET Comput. Digit. Tech. Jaan Raik, Vineeth Govind, Raimund Ubar
2009	—	`conf`	Diagnozer: A laboratory tool for teaching research in diagnosis of electronic systems. MSE Raimund Ubar, Artur Jutman, Jaan Raik, Sergei Kostin, Heinz-Dietrich Wuttke
2009	A	`conf`	Fast extended test access via JTAG and FPGAs. ITC Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar
2009	—	`conf`	High-Level Decision Diagrams based coverage metrics for verification and test. LATW Maksim Jenihhin, Jaan Raik, Anton Chepurov, Uljana Reinsalu, Raimund Ubar
2009	—	`conf`	Investigations of the diagnosibility of digital networks with BIST. LATW Raimund Ubar, Sergei Kostin, Jaan Raik
2009	J	`jnl`	PSL Assertion Checking Using Temporally Extended High-Level Decision Diagrams. J. Electron. Test. Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar
2009	—	`conf`	Structurally synthesized multiple input BDDs for simulation of digital circuits. ICECS Raimund Ubar, Dmitri Mironov, Jaan Raik, Artur Jutman
2009	—	`conf`	Turning JTAG inside out for fast extended test access. LATW Sergei Devadze, Artur Jutman, Igor Aleksejev, Raimund Ubar
2008	C	`conf`	Calculation of LFSR Seed and Polynomial Pair for BIST Applications. DDECS Artur Jutman, Anton Tsertov, Raimund Ubar
2008	C	`conf`	Code Coverage Analysis using High-Level Decision Diagrams. DDECS Jaan Raik, Uljana Reinsalu, Raimund Ubar, Maksim Jenihhin, Peeter Ellervee
2008	Misc	`conf`	Distributed Approach for Genetic Test Generation in the Field of Digital Electronics. IDC Eero Ivask, Jaan Raik, Raimund Ubar
2008	J	`jnl`	Embedded fault diagnosis in digital systems with BIST. Microprocess. Microsystems Raimund Ubar, Sergei Kostin, Jaan Raik
2008	C	`conf`	Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. DSD Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz
2008	—	`conf`	Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. DELTA Raimund Ubar, Sergei Devadze, Maksim Jenihhin, Jaan Raik, Gert Jervan, Peeter Ellervee
2008	J	`jnl`	Hybrid BIST optimization using reseeding and test set compaction. Microprocess. Microsystems Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar
2008	J	`jnl`	Mixed hierarchical-functional fault models for targeting sequential cores. J. Syst. Archit. Jaan Raik, Raimund Ubar, Taavi Viilukas, Maksim Jenihhin
2008	—	`conf`	Parallel fault backtracing for calculation of fault coverage. ASP-DAC Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2008	—	`conf`	Reseeding using compaction of pre-generated LFSR sub-sequences. ICECS Artur Jutman, Igor Aleksejev, Jaan Raik, Raimund Ubar
2008	B	`conf`	Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation. ETS Maksim Jenihhin, Jaan Raik, Anton Chepurov, Raimund Ubar
2008	J	`jnl`	Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols. IET Comput. Digit. Tech. Tomas Bengtsson, Shashi Kumar, Raimund Ubar, Artur Jutman, Zebo Peng
2008	—	`conf`	Untestable Fault Identification in Sequential Circuits Using Model-Checking. ATS Jaan Raik, Hideo Fujiwara, Raimund Ubar, Anna Krivenko
2008	C	`conf`	Web-Based Framework for Parallel Distributed Test. DDECS Eero Ivask, Jaan Raik, Raimund Ubar
2007	J	`jnl`	FPGA-based fault emulation of synchronous sequential circuits. IET Comput. Digit. Tech. Peeter Ellervee, Jaan Raik, Kalle Tammemäe, Raimund Ubar
2007	C	`conf`	Fault Diagnosis in Integrated Circuits with BIST. DSD Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evartson, Harri Lensen
2007	C	`conf`	Hierarchical Identification of Untestable Faults in Sequential Circuits. DSD Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kruus
2007	C	`conf`	Hybrid BIST Optimization Using Reseeding and Test Set Compaction. DSD Gert Jervan, Elmet Orasson, Helena Kruus, Raimund Ubar
2007	C	`conf`	Layout to Logic Defect Analysis for Hierarchical Test Generation. DDECS Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski
2007	J	`jnl`	Learning Digital Test and Diagnostics via Internet. Int. J. Online Eng. Raimund Ubar, Artur Jutman, Margus Kruus, Elmet Orasson, Sergei Devadze, Heinz-Dietrich Wuttke
2007	—	`conf`	Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems. SIES Gert Jervan, Helena Kruus, Elmet Orasson, Raimund Ubar
2007	B	`conf`	Test Configurations for Diagnosing Faulty Links in NoC Switches. ETS Jaan Raik, Raimund Ubar, Vineeth Govind
2007	B	`conf`	Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. ETS Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman
2006	—	`conf`	An External Test Approach for Network-on-a-Chip Switches. ATS Jaan Raik, Vineeth Govind, Raimund Ubar
2006	—	`conf`	DefSim: CMOS Defects on Chip for Research and Education. LATW Witold A. Pleskacz, Tomasz Borejko, Andrzej Walkanis, Viera Stopjaková, Artur Jutman, Raimund Ubar
2006	—	`conf`	Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs. LATW Sergei Devadze, Jaan Raik, Artur Jutman, Raimund Ubar
2006	C	`conf`	High-Level Decision Diagram based Fault Models for Targeting FSMs. DSD Jaan Raik, Raimund Ubar, Taavi Viilukas
2006	C	`conf`	Off-Line Testing of Delay Faults in NoC Interconnects. DSD Tomas Bengtsson, Artur Jutman, Shashi Kumar, Raimund Ubar, Zebo Peng
2006	C	`ed.`	Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006 DDECS Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubátová, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jirí Bucek
2006	J	`jnl`	Test Time Minimization for Hybrid BIST of Core-Based Systems. J. Comput. Sci. Technol. Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
2005	J	`jnl`	A New Testability Calculation Method to Guide RTL Test Generation. J. Electron. Test. Jaan Raik, Tanel Nõmmeots, Raimund Ubar
2005	C	`conf`	An Educational Environment for Digital Testing: Hardware, Tools, and Web-Based Runtime Platform. DSD Artur Jutman, Jaan Raik, Raimund Ubar, V. Vislogubov
2005	B	`conf`	DOT: new deterministic defect-oriented ATPG tool. ETS Jaan Raik, Raimund Ubar, Joachim Sudbrock, Wieslaw Kuzmicz, Witold A. Pleskacz
2005	C	`conf`	Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. DSD Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz
2005	Misc	`conf`	Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. EDCC Jaan Raik, Raimund Ubar, Sergei Devadze, Artur Jutman
2005	B	`conf`	Energy minimization for hybrid BIST in a system-on-chip test environment. ETS Raimund Ubar, Tatjana Shchenova, Gert Jervan, Zebo Peng
2005	C	`conf`	Improved Fault Emulation for Synchronous Sequential Circuits. DSD Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, Raimund Ubar
2004	—	`conf`	Asynchronous e-learning resources for hardware design issues. CompSysTech Artur Jutman, Alexander Sudnitson, Raimund Ubar, Heinz-Dietrich Wuttke
2004	J	`jnl`	Conference Reports. IEEE Des. Test Comput. Vladimir Hahanov, Raimund Ubar, Subhasish Mitra
2004	—	`conf`	Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting. DELTA Raimund Ubar, Maksim Jenihhin
2004	—	`conf`	Web-Based Environment for Digital Electronics Test Tools. Virtual Enterprises and Collaborative Networks Eero Ivask, Jaan Raik, Raimund Ubar, André Schneider
2003	C	`conf`	Back-Traced Deductive-Parallel Fault Simulation for Digital Systems. DSD Vladimir Hahanov, Raimund Ubar, Stanley Hyduke
2003	J	`jnl`	Conference Reports. IEEE Des. Test Comput. Vladimir Hahanov, Raimund Ubar
2003	J	`jnl`	Design Error Diagnosis with Re-Synthesis in Combinational Circuits. J. Electron. Test. Raimund Ubar
2003	—	`conf`	Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture. DFT Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
2003	—	`conf`	Test Time Minimization for Hybrid BIST of Core-Based Systems. Asian Test Symposium Gert Jervan, Petru Eles, Zebo Peng, Raimund Ubar, Maksim Jenihhin
2003	—	`ch.`	Testing Strategies for Networks on Chip. Networks on Chip Raimund Ubar, Jaan Raik
2002	—	`conf`	A Hybrid BIST Architecture and Its Optimization for SoC Testing. ISQED Gert Jervan, Zebo Peng, Raimund Ubar, Helena Kruus
2002	—	`conf`	Fast static compaction of tests composed of independent sequences: basic properties and comparison of methods. ICECS Jaan Raik, Artur Jutman, Raimund Ubar
2002	J	`jnl`	Hierarchical test generation for combinational circuits with real defects coverage. Microelectron. Reliab. T. Cibáková, Mária Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
2002	C	`conf`	Integrated Design and Test Generation Under Internet Based Environment MOSCITO. DSD André Schneider, Karl-Heinz Diener, Eero Ivask, Raimund Ubar, Elena Gramatová, Thomas Hollstein, Wieslaw Kuzmicz, Zebo Peng
2002	A	`conf`	Internet-Based Collaborative Test Generation with MOSCITO. DATE André Schneider, Karl-Heinz Diener, Eero Ivask, Jaan Raik, Raimund Ubar, P. Miklos, T. Cibáková, Elena Gramatová
2002	—	`conf`	Multi-Level Fault Simulation of Digital Systems on Decision Diagrams. DELTA Raimund Ubar, Jaan Raik, Eero Ivask, Marina Brik
2002	—	`conf`	Practical works for on-line teaching design and test of digital circuits. ICECS Artur Jutman, Raimund Ubar, Vladimir Hahanov, O. Skvortsova
2002	—	`conf`	Testability Calculation for Digital Circuits with Decision Diagrams. LATW Raimund Ubar
2001	—	`conf`	Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. ISQED Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
2001	—	`conf`	Design Error Diagnosis in Scan-Path Designs. LATW Raimund Ubar
2001	C	`conf`	Fast Test Cost Calculation for Hybrid BIST in Digital Systems. DSD Elmet Orasson, Rein Raidma, Raimund Ubar, Gert Jervan, Zebo Peng
2001	J	`jnl`	Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. Microelectron. Reliab. Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
2001	A	`conf`	Timing simulation of digital circuits with binary decision diagrams. DATE Raimund Ubar, Artur Jutman, Zebo Peng
2000	C	`conf`	Back-tracing and event-driven techniques in high-level simulation with decision diagrams. ISCAS Raimund Ubar, Jaan Raik, Adam Morawiec
2000	A	`conf`	Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. DATE Adam Morawiec, Raimund Ubar, Jaan Raik
2000	—	`conf`	Efficient Hierarchical Approach to Test Generation for Digital Systems. ISQED Raimund Ubar, Jaan Raik
2000	J	`jnl`	Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. J. Electron. Test. Jaan Raik, Raimund Ubar
2000	—	`conf`	Hierarchical defect-oriented fault simulation for digital circuits. ETW Mykola Blyzniuk, T. Cibáková, Elena Gramatová, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
2000	—	`conf`	Test Cost Minimization for Hybrid Bist. DFT Gert Jervan, Zebo Peng, Raimund Ubar
1999	A	`conf`	Cycle-based Simulation with Decision Diagrams. DATE Raimund Ubar, Jaan Raik, Adam Morawiec
1999	—	`conf`	Design Error Diagnosis in Digital Circuits without Error Model. VLSI Raimund Ubar, Dominique Borrione
1999	—	`conf`	High-level path activation technique to speed up sequential circuit test generation. ETW Jaan Raik, Raimund Ubar
1999	A	`conf`	Sequential Circuit Test Generation Using Decision Diagram Models. DATE Jaan Raik, Raimund Ubar
1998	—	`conf`	Generation of Tests for the Localization of Single Gate Design Errors in Combinational Circuits using the Stuck-at Fault Model. SBCCI Raimund Ubar, Dominique Borrione
1997	—	`conf`	A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. ED&TC Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar
1997	—	`conf`	Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar
1996	Misc	`conf`	Multi-Level Test Generation and Fault Diagnosis for Finite State Machines. EDCC Raimund Ubar, Marina Brik
1996	J	`jnl`	Test Synthesis with Alternative Graphs. IEEE Des. Test Comput. Raimund Ubar
1994	Misc	`conf`	Test Generation for Digital Systems Based on Alternative Graphs. EDCC Raimund Ubar