Rahul Shrestha

64 papers C 6Misc 10Journal 32Unranked 16
YearRankTypeTitle / Venue / Authors
2026 Misc conf
A Novel VLSI Architecture and FPGA Implementation of Hardware-Efficient Mfocuss-Based Wideband Spectrum Sensor for Dynamic Spectrum Access.
VLSID
Aayush Shrivas, Rahul Shrestha
2026 Misc conf
Design and FPGA Implementation of Power and Area Efficient Multi-Stage Accelerator for Depthwise Separable Convolutions.
VLSID
Srishti Misra, Rahul Shrestha
2026 — conf
Hardware Architecture of Dual Sensing Time and Reconfigurable Cooperative Spectrum Sensor for Dynamic Spectrum Access in Cognitive Radio Network.
NCC
Divya Agrawal, Rahul Shrestha
2025 — conf
Automated Image Colorization using Generative Adversarial Networks.
ICACS
Jaisal Sharma, Rahul Shrestha, Dibakar Raj Pant, Jukka-Pekka Skon, Jukka Heikkonen, Rajeev Kanth
2025 Misc conf
CRIS-b: A High-Speed Unified Modulo Reduction Algorithm and Hardware Architecture for CRYSTALS-Kyber.
VLSID
Alip Majumdar, Rahul Shrestha
2025 J jnl
Energy-Preserving Indirect-Feedback for Wireless Power Transfer: Algorithm and Hardware Architecture.
IEEE Trans. Green Commun. Netw.
Siddhartha Sarma, Rahul Shrestha, Rohit B. Chaurasiya
2024 J jnl
A New Hardware-Efficient and Low Sensing-Time Cooperative Spectrum-Sensor for High-Throughput Cognitive-Radio Network.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shakti Singh, Rahul Shrestha
2024 J jnl
Energy-Efficient and High-Throughput CNN Inference Engine Based on Memory-Sharing and Data-Reusing for Edge Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Md. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury
2024 J jnl
High-Throughput and Hardware-Efficient ASIC-Chip Fabrication of Reconfigurable LDPC/Polar Decoder for mMTC and URLLC 5G-NR Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Anuj Verma, Rahul Shrestha
2024 Misc conf
Low-Complexity lassification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator.
VLSID
Md. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury
2024 J jnl
Ultra-Low Sensing-Time and Hardware-Efficient Spectrum Sensor for Data Fusion-Based Cooperative Cognitive-Radio Network.
IEEE Trans. Consumer Electron.
Shakti Singh, Rahul Shrestha
2024 J jnl
VLSI Architectures and Hardware Implementation of Ultra Low-Latency and Area-Efficient Pietra-Ricci Index Detector for Spectrum Sensing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Elivander J. T. Pereira, Dayan Adionel Guimarães, Rahul Shrestha
2023 Misc conf
Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems.
VLSID
Meghvern Pathak, Rahul Shrestha
2023 J jnl
Hardware-Efficient and Short Sensing-Time Multicoset-Sampling Based Wideband Spectrum Sensor for Cognitive Radio Network.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rahul Sharma, Rahul Shrestha, Satinder K. Sharma
2023 J jnl
Low Computational-Complexity SOMS-Algorithm and High-Throughput Decoder Architecture for QC-LDPC Codes.
IEEE Trans. Veh. Technol.
Anuj Verma, Rahul Shrestha
2023 J jnl
Resource-Efficient Low-Latency Modified Pietra-Ricci Index Detector for Spectrum Sensing in Cognitive Radio Networks.
IEEE Trans. Veh. Technol.
Dayan Adionel Guimarães, Elivander J. T. Pereira, Rahul Shrestha
2022 — conf
A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications.
ISVLSI
Md. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury
2022 J jnl
A System-Level Design & FPGA Implementation for Real-Time Interception & Monitoring the Frequency-Agile Communication Signal.
J. Signal Process. Syst.
Lalit Kumar, Rahul Shrestha
2022 J jnl
An Uninterrupted Processing Technique-Based High-Throughput and Energy-Efficient Hardware Accelerator for Convolutional Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Md. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury
2022 J jnl
Design and ASIC-Implementation of Hardware-Efficient Cooperative Spectrum-Sensor for Data Fusion-Based Cognitive Radio Network.
IEEE Trans. Consumer Electron.
Rohit B. Chaurasiya, Rahul Shrestha
2022 J jnl
Hardware-Efficient VLSI Architecture and ASIC Implementation of GRCR-Based Cooperative Spectrum Sensor for Cognitive-Radio Network.
IEEE Trans. Very Large Scale Integr. Syst.
Rohit B. Chaurasiya, Rahul Shrestha
2022 — conf
High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems.
ISVLSI
Kumari Suravi, Rahul Shrestha
2022 J jnl
Low-Latency and Reconfigurable VLSI-Architectures for Computing Eigenvalues and Eigenvectors Using CORDIC-Based Parallel Jacobi Method.
IEEE Trans. Very Large Scale Integr. Syst.
Rahul Sharma, Rahul Shrestha, Satinder K. Sharma
2022 J jnl
Selective register-file cache: an energy saving technique for embedded processor architecture.
Des. Autom. Embed. Syst.
Sumanth Gudaparthi, Rahul Shrestha
2021 J jnl
A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Rahul Shrestha
2021 J jnl
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network.
IEEE Trans. Very Large Scale Integr. Syst.
Rohit B. Chaurasiya, Rahul Shrestha
2021 J jnl
Area-Efficient and Scalable Data-Fusion Based Cooperative Spectrum Sensor for Cognitive Radio.
IEEE Trans. Circuits Syst. II Express Briefs
Rohit B. Chaurasiya, Rahul Shrestha
2021 C conf
Hardware-Efficient ASIC Implementation of Eigenvalue Based Spectrum Sensor Reconfigurable-Architecture for Cooperative Cognitive-Radio Network.
ISCAS
Rohit B. Chaurasiya, Rahul Shrestha
2021 J jnl
Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture.
IEEE Trans. Circuits Syst. II Express Briefs
Anuj Verma, Rahul Shrestha
2020 Misc conf
A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio.
VLSID
Anuj Verma, Rahul Shrestha
2020 C conf
A New VLSI Architecture of Next-Generation QC-LDPC Decoder for 5G New-Radio Wireless-Communication Standard.
ISCAS
Anuj Verma, Rahul Shrestha
2020 C conf
A Short Sensing-Time Cyclostationary Feature Detection Based Spectrum Sensor for Cognitive Radio Network.
ISCAS
Rahul Shrestha, Shubham Sanjay Telgote
2020 J jnl
Fast Sensing-Time and Hardware-Efficient Eigenvalue-Based Blind Spectrum Sensors for Cognitive Radio Network.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Rohit B. Chaurasiya, Rahul Shrestha
2019 J jnl
Hardware-Efficient and Fast Sensing-Time Maximum-Minimum-Eigenvalue-Based Spectrum Sensor for Cognitive Radio Network.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rohit B. Chaurasiya, Rahul Shrestha
2019 C conf
Hardware-Efficient and Low Sensing-Time VLSI-Architecture of MED Based Spectrum Sensor for Cognitive Radio.
ISCAS
Rohit B. Chaurasiya, Rahul Shrestha
2019 J jnl
High-Speed and Hardware-Efficient Successive Cancellation Polar-Decoder.
IEEE Trans. Circuits Syst. II Express Briefs
Rahul Shrestha, Abhijit Sahoo
2019 Misc conf
High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New Radio.
VLSID
Rahul Shrestha, Pooja Bansal, Srikant Srinivasan
2018 J jnl
Hardware implementation and VLSI design of spectrum sensor for next-generation LTE-A cognitive-radio wireless network.
IET Circuits Devices Syst.
Mahesh S. Murty, Rahul Shrestha
2018 Misc conf
Hardware-Efficient and Wide-Band Frequency-Domain Energy Detector for Cognitive-Radio Wireless Network.
VLSID
Mahesh S. Murty, Rahul Shrestha
2018 C conf
Parameterized Posit Arithmetic Hardware Generator.
ICCD
Rohit Chaurasiya, John L. Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers
2018 — conf
Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices.
VDAT
Rahul Shrestha, Ashutosh Sharma
2018 J jnl
Reconfigurable and Memory-Efficient Cyclostationary Spectrum Sensor for Cognitive-Radio Wireless Networks.
IEEE Trans. Circuits Syst. II Express Briefs
Mahesh S. Murty, Rahul Shrestha
2018 C conf
VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates.
VLSI-SoC
Rahul Shrestha, Ashutosh Sharma
2017 — conf
A New Multi-objective Hardware-Software-Partitioning Algorithmic Approach for High Speed Applications.
VDAT
Naman Govil, Rahul Shrestha, Shubhajit Roy Chowdhury
2017 — conf
A self-bandwidth switching & area-efficient PLL using multiplexer-controlled frequency selector.
ISED
B. Dinesh Kumar, Sumit Pandey, Puneet Arora, Rahul Shrestha
2017 — conf
Embedded Hardware Prototype for Gas Detection and Monitoring System in Android Mobile Platform.
iNIS
Rahul Kurzekar, Hardik Arora, Rahul Shrestha
2017 — conf
Energy-Efficient VLSI Architecture & Implementation of Bi-modal Multi-banked Register-File Organization.
VDAT
Sumanth Gudaparthi, Rahul Shrestha
2017 — conf
High-speed and low-power VLSI-architecture for inexact speculative adder.
VLSI-DAT
Rahul Shrestha
2017 J jnl
PGMA: An algorithmic approach for multi-objective hardware software partitioning.
Microprocess. Microsystems
Naman Govil, Rahul Shrestha, Shubhajit Roy Chowdhury
2016 — conf
Cognitive-radio wireless-sensor based on energy detection with improved accuracy: Performance and hardware perspectives.
VDAT
Rahul Shrestha, Vinay Swargam, Mahesh S. Murty
2016 Misc conf
Design and Implementation of Area-Efficient and Low-Power Configurable Booth-Multiplier.
VLSID
Rahul Shrestha, Utkarsh Rastogiy
2016 J jnl
Memory-Reduced Maximum A Posteriori Probability Decoding for High-Throughput Parallel Turbo Decoders.
Circuits Syst. Signal Process.
Rahul Shrestha, Roy Paily
2016 J jnl
Multi-standard high-throughput and low-power quasi-cyclic low density parity check decoder for worldwide interoperability for microwave access and wireless fidelity standards.
IET Circuits Devices Syst.
Vijaya Kumar Kanchetla, Rahul Shrestha, Roy Paily
2016 — conf
VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation.
ISVLSI
Mahesh S. Murty, Rahul Shrestha
2015 J jnl
Comparative Study of Simplified MAP Algorithms and an Implementation of Non-Parallel-Radix-2 Turbo Decoder.
J. Signal Process. Syst.
Rahul Shrestha, Roy P. Paily
2015 J jnl
High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule.
IEEE Trans. Circuits Syst. I Regul. Pap.
Sachin Kumawat, Rahul Shrestha, Nikunj Daga, Roy P. Paily
2015 — conf
Machine learning for the activation of contraflows during hurricane evacuation.
GHTC
John Welsey Burris, Rahul Shrestha, Bibek Gautam, Bibidh Bista
2015 J jnl
VLSI Design and Hardware Implementation of High-Speed Energy-Efficient Logarithmic-MAP Decoder.
J. Low Power Electron.
Rahul Shrestha, Roy P. Paily
2014 — conf
Hardware Implementation and Testing of Log-MAPP Decoder Based on Novel Un-grouped Sliding-Window Technique.
ISED
Rahul Shrestha, Roy Paily
2014 J jnl
High-Throughput Turbo Decoder With Parallel Architecture for LTE Wireless Communication Standards.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rahul Shrestha, Roy P. Paily
2013 — conf
A novel state metric normalization technique for high-throughput maximum-a-posteriori-probability decoder.
ICACCI
Rahul Shrestha, Roy P. Paily
2013 Misc conf
Design and Implementation of a High Speed MAP Decoder Architecture for Turbo Decoding.
VLSI Design
Rahul Shrestha, Roy P. Paily
2013 J jnl
Performance and throughput analysis of turbo decoder for the physical layer of digitalvideo-broadcasting-satellite-services-tohandhelds standard.
IET Commun.
Rahul Shrestha, Roy P. Paily
2012 — conf
Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding.
VDAT
Rahul Shrestha, Roy P. Paily