Rahul M. Rao - RankMe

44 papers A* 1A 8B 1C 2Misc 5Journal 12Unranked 14

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	IBM Telum II Microprocessor: 5.5 GHz With On-Die AI and Data Processing, and Design-Technology Co-Optimizations for Power, Area, and Reliability. IEEE J. Solid State Circuits Gerald Strevig, David Wolpert, Leon Sigal, Bill Huott, Mark Cichanowski, Noam Jungmann, Michael A. Sperling, Michael J. Becht, Matthias Pflanz, Daniel Kiss, Simon Büchsenstein, Tobias Werner, Philipp Salz, Michael Romain, Richard E. Serton, Nick Jing, Rajesh Veerabhadraiah, Dureseti Chidambarrao, Robert Arelt, Matt Angyal, Ben Trombley, Arvind Haran, Rahul M. Rao, Christopher J. Berry, Amanda Venton, Elazar Kachir, Andreas Arp
2025	—	`conf`	2.2 IBM Telum II: Next Generation 5.5GHz Microprocessor with On-Die Data Processing Unit and Improved AI Accelerator. ISSCC Gerald Strevig, Christopher J. Berry, Rahul M. Rao, Noam Jungmann, Michael A. Sperling, Michael J. Becht, Eduard Herkel, Matthias Pflanz, Patrick J. Meaney, Michael Romain, Mark Cichanowski, Amanda Venton, David Wolpert, Elazar Kachir, Luke Hopkins, Tim E. Bubb, Andreas Arp, Daniel Kiss, Simon Büchsenstein, Michael H. Wood, Michael Spear, Robert J. Sonnelitter, Rajiv Joshi
2025	—	`conf`	37.1 IBM Telum II Processor Design-Technology Co-Optimizations for Power, Performance, Area, and Reliability. ISSCC David Wolpert, Gerry Strevig, Christopher J. Berry, Leon J. Sigal, Bill Huott, Mark Cichanowski, Matthias Pflanz, Tobias Werner, Philipp Salz, Nick Jinq, Michael Romain, Iris Leefken, Richard E. Serton, Rajesh Veerabhadraiah, Dureseti Chidambarrao, Robert Arelt, Matt Angyal, Ben Trombley, Arvind Haran, Stefan Hougardy, Ben Klotz, Rahul M. Rao
2024	A	`conf`	Late Breaking Results: Scan-Chain Optimization with Constrained Single Linkage Clustering and Geometry-Based Cluster Balancing. DATE George Antony, Gireesh Kumar K. M, Naiju Karim Abdul, Rahul M. Rao
2022	—	`conf`	POWER10™: A 16-Core SMT8 Server Processor With 2TB/s Off-Chip Bandwidth in 7nm Technology. ISSCC Rahul M. Rao, Christopher J. Gonzalez, Eric Fluhr, Abraham Mathews, Andrew Bianchi, Daniel Dreps, David Wolpert, Eric Lai, Gerald Strevig, Glen A. Wiedemeier, Philipp Salz, Ryan Kruse
2022	—	`conf`	Scan Chain Clustering and Optimization with Constrained Clustering and Reinforcement Learning. MLCAD Naiju Karim Abdul, George Antony, Rahul M. Rao, Suriya T. Skariah
2021	A*	`conf`	Energy Efficiency Boost in the AI-Infused POWER10 Processor. ISCA Brian W. Thompto, Dung Q. Nguyen, José E. Moreira, Ramon Bertran, Hans M. Jacobson, Richard J. Eickemeyer, Rahul M. Rao, Michael Goulet, Marcy Byers, Christopher J. Gonzalez, Karthik Swaminathan, Nagu R. Dhanwada, Silvia M. Müller, Andreas Wagner, Satish Kumar Sadasivam, Robert K. Montoye, William J. Starke, Christian G. Zoellin, Michael S. Floyd, Jeffrey Stuecheli, Nandhini Chandramoorthy, John-David Wellman, Alper Buyuktosunoglu, Matthias Pflanz, Balaram Sinharoy, Pradip Bose
2019	J	`jnl`	A Simulation-Based Metric to Guide Glitch Power Reduction in Digital Circuits. IEEE Trans. Very Large Scale Integr. Syst. Shivani Bathla, Rahul M. Rao, Nitin Chandrachoodan
2018	Misc	`conf`	A High Performance Gated Voltage Level Translator with Integrated Multiplexer. VLSID Dharshak B. S., Rahul M. Rao
2018	J	`jnl`	IBM POWER9 circuit design and energy optimization for 14-nm technology. IBM J. Res. Dev. Eric J. Fluhr, Rahul M. Rao, Howard Smith, Alper Buyuktosunoglu, Ramon Bertran Monfort
2018	Misc	`conf`	Impact of Device Aging on Early Mode Failures in Pulsed Latches. VLSID Ankur Shukla, Rahul M. Rao, James D. Warnock
2018	J	`jnl`	The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. IEEE J. Solid State Circuits Christopher J. Gonzalez, Michael S. Floyd, Eric Fluhr, Phillip J. Restle, Daniel Dreps, Michael A. Sperling, Rahul M. Rao, David Hogenmiller, Christos Vezyrtzis, Pierce Chuang, Daniel Lewis, Ricardo Escobar, Vinod Ramadurai, Ryan Kruse, Juergen Pille, Ryan Nett, Pawel Owczarczyk, Joshua Friedrich, Jose Paredes, Timothy Diemoz, Md. Saiful Islam, Donald W. Plass, Paul Muench
2017	—	`conf`	3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4. ISSCC Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam, Juergen Pille, Donald W. Plass
2017	J	`jnl`	Adaptive Bus Encoding for Transition Reduction on Off-Chip Buses With Dynamically Varying Switching Characteristics. IEEE Trans. Very Large Scale Integr. Syst. Sumantra Sarkar, Ayan Biswas, Anindya Sundar Dhar, Rahul M. Rao
2016	A	`conf`	FVCAG: A framework for formal verification driven power modeling and verification. ISLPED Arun Joseph, Spandana Rachamalla, Rahul M. Rao, Anand Haridass, Pradeep Kumar Nalla
2015	J	`jnl`	IBM POWER8 circuit design and energy optimization. IBM J. Res. Dev. Victor V. Zyuban, Joshua Friedrich, Daniel M. Dreps, Jürgen Pille, Donald W. Plass, Phillip J. Restle, Zeynep Toprak Deniz, Matthew M. Ziegler, Sam G. Chu, Md. Saiful Islam, James D. Warnock, Bob Philhower, Rahul M. Rao, Gregory S. Still, David Shan, Eric Fluhr, Jose Paredes, Dieter F. Wendel, Christopher J. Gonzalez, D. Hogenmiller, Ruchir Puri, Scott A. Taylor, Stephen D. Posluszny
2015	—	`conf`	Virtual logic netlist: Enabling efficient RTL analysis. ISQED Spandana Rachamalla, Arun Joseph, Rahul M. Rao, Diwesh Pandey
2013	A	`conf`	Efficient PVT independent abstraction of large IP blocks for hierarchical power analysis. ICCAD Nagu R. Dhanwada, David J. Hathaway, Victor V. Zyuban, Peng Peng, Karl Moody, William W. Dungan, Arun Joseph, Rahul M. Rao, Christopher J. Gonzalez
2013	B	`conf`	Extracting device-parameter variations using a single sensitivity-configurable ring oscillator. ETS Yuma Higuchi, Kenichi Shinkai, Masanori Hashimoto, Rahul M. Rao, Sani R. Nassif
2013	J	`jnl`	Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection. IEEE Trans. Very Large Scale Integr. Syst. Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown
2011	J	`jnl`	SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang
2011	—	`ch.`	Variations: Sources and Characterization. Low-Power Variation-Tolerant Design in Nanometer Silicon Aditya Bansal, Rahul M. Rao
2010	J	`jnl`	Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise. IEEE Trans. Very Large Scale Integr. Syst. Harmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown
2010	—	`conf`	Technology-circuit co-design of asymmetric SRAM cells for read stability improvement. CICC Jae-Joon Kim, Rahul M. Rao, Keunwoo Kim
2009	J	`jnl`	A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry. IEEE J. Solid State Circuits Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim
2009	C	`conf`	A Precise Negative Bias Temperature Instability Sensor using Slew-rate Monitor Circuitry. ISCAS Amlan Ghosh, Richard B. Brown, Rahul M. Rao, Ching-Te Chuang
2009	A	`conf`	A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. ISLPED Amlan Ghosh, Rahul M. Rao, Richard B. Brown
2009	J	`jnl`	Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. Microelectron. Reliab. Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang
2008	—	`conf`	A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement. ISSCC Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim
2008	C	`conf`	Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. ISCAS Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang
2008	Misc	`conf`	On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. VLSI Design Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown
2008	—	`conf`	On-Chip Process Variation Detection and Compensation Using Delay and Slew-Rate Monitoring Circuits. ISQED Amlan Ghosh, Rahul M. Rao, Ching-Te Chuang, Richard B. Brown
2007	J	`jnl`	Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. IEEE Trans. Very Large Scale Integr. Syst. Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown
2005	—	`conf`	Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength. SoCC Harmander Singh Deogun, Dennis Sylvester, Rahul M. Rao, Kevin J. Nowka
2005	—	`conf`	Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. ISQED Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka
2005	—	`conf`	Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown
2005	—	`conf`	Power-aware global signaling strategies. ISCAS (1) Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif
2004	Misc	`conf`	Analysis and Optimization of Enhanced MTCMOS Scheme. VLSI Design Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown
2004	A	`conf`	Approaches to run-time and standby mode leakage reduction in global buses. ISLPED Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif
2003	A	`conf`	A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits. ICCAD Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard B. Brown
2003	—	`conf`	Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies. ESSCIRC Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown
2003	A	`conf`	Efficient techniques for gate leakage estimation. ISLPED Rahul M. Rao, Jeffrey L. Burns, Anirudh Devgan, Richard B. Brown
2003	A	`conf`	Leakage and leakage sensitivity computation for combinational circuits. ISLPED Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns
1978	Misc	`conf`	Frequency estimation by linear prediction. ICASSP Leland B. Jackson, Donald W. Tufts, Frank K. Soong, Rahul M. Rao