Raghu Sastry

14 papers A* 1C 2Misc 1Journal 7Unranked 3
YearRankTypeTitle / Venue / Authors
1998 J jnl
A VLSI Architecture for Approximate Tree Matching.
IEEE Trans. Computers
Raghu Sastry, N. Ranganathan
1998 J jnl
SMAC: A VLSI Architecture for Scene Matching.
Real Time Imaging
N. Ranganathan, Raghu Sastry, Raguveer Venkatesan
1996 — conf
A 9.6 GigaByte/s Throughput Plesiochronous Routing Chip.
COMPCON
Albert Mu, Jeff Larson, Raghu Sastry, Thomas Wicki, Winfried W. Wilcke
1995 A* conf
A VLSI Architecture for Computer the Tree-to-Tree Distance.
HPCA
Raghu Sastry, N. Ranganathan
1995 J jnl
CASM: A VLSI Chip for Approximate String Matching.
IEEE Trans. Pattern Anal. Mach. Intell.
Raghu Sastry, N. Ranganathan, Klinton Remedios
1995 J jnl
PMAC: A Polygon Matching Chip.
Int. J. Pattern Recognit. Artif. Intell.
Raghu Sastry, N. Ranganathan
1995 J jnl
VLSI Architectures for High-Speed Range Estimation.
IEEE Trans. Pattern Anal. Mach. Intell.
Raghu Sastry, N. Ranganathan, Ramesh C. Jain
1994 J jnl
VLSI Architectures for Pattern Matching.
Int. J. Pattern Recognit. Artif. Intell.
N. Ranganathan, Raghu Sastry
1993 C conf
A Systolic Array for Approximate String Matching.
ICCD
Raghu Sastry, N. Ranganathan
1993 Misc conf
Hardware Algorithms for Polygon Matching.
VLSI Design
Raghu Sastry, N. Ranganathan, Horst Bunke
1993 C conf
SMAC: A Scene Matching Chip.
ICCD
N. Ranganathan, Raghu Sastry, Raguveer Venkatesan, Joseph W. Yoder, David C. Keezer
1993 — conf
VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis.
IPPS
Raghu Sastry, N. Ranganathan, Ramesh C. Jain
1993 J jnl
VLSI architectures for polygon recognition.
IEEE Trans. Very Large Scale Integr. Syst.
Raghu Sastry, N. Ranganathan, Horst Bunke
1992 — conf
A VLSI architecture for hierarchical scene matching.
ICPR (4)
R. Venkatesan, Raghu Sastry, N. Ranganathan