Ragh Kuttappa

26 papers A* 1A 3C 10Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2025 — conf
A High-Performance Passive Base System for Distributed AI/Media Acceleration.
CICC
Ragh Kuttappa, Jainaveen Sundaram, Srivatsa Rangachar Srinivasa, Paolo A. Aseron, Gauthaman Murali, Vinayak Honkote, Prerna Budhkar, Dileep Kurian, Ronald Kalim, Thomas P. Thomas, Anuradha Srinivasan, Tanay Karnik
2025 J jnl
A Synchronous 13.1 GHz Backside Resonant Clocking Mesh Implemented on a Graphics Core in an 18A Class Technology.
IEEE Solid State Circuits Lett.
Ragh Kuttappa, Vinayak Honkote, Amreesh Rao, Gaurav Kamalkar, Kailash Chandrashekar, Eric Finley, Chaitanya Sankuratri, Faran Rafiq, Robert Orton, Nils Hernandez, Anuradha Srinivasan, Tanay Karnik
2025 A conf
Invited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D Integration.
ICCAD
Gauthaman Murali, Mudit Bhargava, Shairfe Salahuddin, Zhichao Chen, Archana Pandey, Srivatsa Rangachar Srinivasa, Prerna Budhkar, Ragh Kuttappa, Vinayak Honkote, Prashanth Sakthi, Myung-Hee Na, Tanay Karnik
2025 — conf
System-Level Validation Across Multiple Platforms to build a Robust 2.5D Multi Foundry Chiplet Solution.
ACM Great Lakes Symposium on VLSI
Srivatsa Rangachar Srinivasa, Dileep Kurian, Paolo A. Aseron, Prerna Budhkar, Vinayak Honkote, Dan Lake, Jaykant Timbadiya, Satish Yada, Suresh Kadavakollu, James Greensky, Gauthaman Murali, Anuradha Srinivasan, Ragh Kuttappa, Tanay Karnik
2024 — conf
A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems.
VLSI Technology and Circuits
Vinayak Honkote, Ragh Kuttappa, Jainaveen Sundaram, Satish Yada, Chinnusamy Kalimuthu, Juhi Patil, Richard Lee, Cristan Paulino, Paolo A. Aseron, Trang Nguyen, Amreesh Rao, Dileep Kurian, Mingming Xu, Yan Song, Tanay Karnik, Anuradha Srinivasan, Vivek De
2024 C conf
Design Automation for Charge Recovery Logic.
ISCAS
Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin
2024 C conf
High-Speed Phase-Based Computing.
ISCAS
Nicholas Sica, Ragh Kuttappa, Vinayak Honkote, Baris Taskin
2022 C conf
A 0.45 pJ/bit 20 Gb/s/Wire Parallel Die-to-Die Interface with Rotary Traveling Wave Oscillators.
ISCAS
Ragh Kuttappa, Baris Taskin
2022 J jnl
Multiphase Digital Low-Dropout Regulators.
IEEE Trans. Very Large Scale Integr. Syst.
Ragh Kuttappa, Longfei Wang, Selçuk Köse, Baris Taskin
2022 C conf
Resonant Rotary Clock Synchronization with Active and Passive Silicon Interposer.
ISCAS
Ragh Kuttappa, Baris Taskin, Vinayak Honkote, Satish Yada, Jainaveen Sundaram, Dileep Kurian, Tanay Karnik, Anuradha Srinivasan
2021 J jnl
Resonant Clock Synchronization With Active Silicon Interposer for Multi-Die Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano
2021 — conf
Scalable Resonant Power Clock Generation for Adiabatic Logic Design.
ISVLSI
Ragh Kuttappa, Leo Filippini, Nicholas Sica, Baris Taskin
2020 C conf
Comprehensive Low Power Adiabatic Circuit Design with Resonant Power Clocking.
ISCAS
Ragh Kuttappa, Steven Khoa, Leo Filippini, Vasil Pano, Baris Taskin
2020 C conf
FinFET - Based Low Swing Rotary Traveling Wave Oscillators.
ISCAS
Ragh Kuttappa, Baris Taskin
2020 A* conf
SnackNoC: Processing in the Communication Layer.
HPCA
Karthik Sangaiah, Michael Lui, Ragh Kuttappa, Baris Taskin, Mark Hempstead
2019 — conf
3D NoCs with active interposer for multi-die systems.
NOCS
Vasil Pano, Ragh Kuttappa, Baris Taskin
2019 — conf
Distributed Digital Low-Dropout Regulators with Phase Interleaving for On-Chip Voltage Noise Mitigation.
SLIP
Longfei Wang, Ragh Kuttappa, Baris Taskin, Selçuk Köse
2019 J jnl
FOPAC: Flexible On-Chip Power and Clock.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ragh Kuttappa, Selçuk Köse, Baris Taskin
2019 C conf
Low Swing - Low Frequency Rotary Traveling Wave Oscillators.
ISCAS
Ragh Kuttappa, Scott Lerner, Leo Filippini, Baris Taskin
2019 A conf
Robust Low Power Clock Synchronization for Multi-Die Systems.
ISLPED
Ragh Kuttappa, Baris Taskin, Scott Lerner, Vasil Pano, Ioannis Savidis
2019 J jnl
RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ragh Kuttappa, Adarsha Balaji, Vasil Pano, Baris Taskin, Hamid Mahmoodi
2018 C conf
Low Frequency Rotary Traveling Wave Oscillators.
ISCAS
Ragh Kuttappa, Baris Taskin
2017 A conf
Reconfigurable threshold logic gates using optoelectronic capacitors.
DATE
Ragh Kuttappa, Lunal Khuon, Bahram Nabet, Baris Taskin
2017 C conf
Stability of Rotary Traveling Wave Oscillators under process variations and NBTI.
ISCAS
Ragh Kuttappa, Leo Filippini, Scott Lerner, Baris Taskin
2016 C conf
Comparative analysis of robustness of spin transfer torque based look up tables under process variations.
ISCAS
Ragh Kuttappa, Houman Homayoun, Hassan Salmani, Hamid Mahmoodi
2016 J jnl
Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging.
Microelectron. Reliab.
Ragh Kuttappa, Houman Homayoun, Hassan Salmani, Hamid Mahmoodi