Rafael Trapani Possignolo

18 papers A* 3B 3C 4Journal 4Unranked 2

Year	Rank	Type	Title / Venue / Authors
2020	J	`jnl`	LiveHD: A Productive Live Hardware Development Flow. IEEE Micro Sheng-Hong Wang, Rafael Trapani Possignolo, Haven Blake Skinner, Jose Renau
2020	B	`conf`	LiveSim: A Fast Hot Reload Simulator for HDLs. ISPASS Haven Blake Skinner, Rafael Trapani Possignolo, Sheng-Hong Wang, Jose Renau
2019	A*	`conf`	EMI Architectural Model and Core Hopping. MICRO Daphne I. Gorman, Rafael Trapani Possignolo, Jose Renau
2019	A*	`conf`	SMatch: Structural Matching for Fast Resynthesis in FPGAs. DAC Rafael Trapani Possignolo, Jose Renau
2018	—	`ch.`	Automated Pipeline Transformations with Fluid Pipelines. Advanced Logic Synthesis Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau
2018	J	`jnl`	GPU NTC Process Variation Compensation With Voltage Stacking. IEEE Trans. Very Large Scale Integr. Syst. Rafael Trapani Possignolo, Elnaz Ebrahimi, Ehsan K. Ardestani, Alamelu Sankaranarayanan, José Luis Briz, Jose Renau
2018	—	`—`	Improving the Productivity of Hardware Design. Rafael Trapani Possignolo
2017	C	`conf`	Level shifter design for voltage stacking. ISCAS Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau
2017	C	`conf`	Liam: an actor based programming model for HDLs. MEMOCODE Haven Blake Skinner, Rafael Trapani Possignolo, Jose Renau
2017	A*	`conf`	LiveSynth: Towards an Interactive Synthesis Flow. DAC Rafael Trapani Possignolo, Jose Renau
2016	B	`conf`	Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs. FPL Ilya Ganusov, Henri Fraisse, Aaron Ng, Rafael Trapani Possignolo, Sabya Das
2016	C	`conf`	Fluid Pipelines: Elastic circuitry meets Out-of-Order execution. ICCD Rafael Trapani Possignolo, Elnaz Ebrahimi, Haven Blake Skinner, Jose Renau
2016	—	`conf`	LiveSynth: Towards an interactive synthesis flow. Hot Chips Symposium Rafael Trapani Possignolo, Jose Renau
2016	J	`jnl`	Managing Mismatches in Voltage Stacking with CoreUnfolding. ACM Trans. Archit. Code Optim. Ehsan K. Ardestani, Rafael Trapani Possignolo, José Luis Briz, Jose Renau
2016	C	`conf`	SRAM voltage stacking. ISCAS Elnaz Ebrahimi, Rafael Trapani Possignolo, Jose Renau
2015	J	`jnl`	Quantum-assisted QD-CFS signatures. J. Comput. Syst. Sci. Rafael Trapani Possignolo, Cíntia Borges Margi, Paulo S. L. M. Barreto
2012	B	`conf`	A Quantum-classical Hybrid Architecture for Security Algorithms Acceleration. TrustCom Rafael Trapani Possignolo, Cíntia B. Margi
2009	—	`conf`	Optimized joint NARX ANN - embedded processor design methodology. ICECS Rafael Trapani Possignolo, Omar Hammami