| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2009 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2009 | J | jnl |
Integr.
|
| 2009 | J | jnl |
IEEE Des. Test Comput.
|
| 2008 | C | conf |
Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits.
DSD
|
| 2007 | A | conf |
DATE
|
| 2007 | J | jnl |
CoRR
|
| 2007 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2006 | J | jnl |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
|
| 2006 | A | conf |
DATE
|
| 2005 | — | conf |
ASP-DAC
|
| 2005 | A | conf |
DATE
|
| 2005 | A | conf |
ICCAD
|
| 2004 | A | conf |
DATE
|
| 2004 | — | conf |
ISVLSI
|
| 2003 | — | conf |
PATMOS
|