Rafael Gadea Gironés

28 papers B 4C 1Misc 1Journal 12Unranked 9
YearRankTypeTitle / Venue / Authors
2023 J jnl
Task parallelism-based architectures on FPGA to optimize the energy efficiency of AI at the edge.
Microprocess. Microsystems
Rafael Gadea Gironés, Jorge D. Fe, José María Monzó
2018 J jnl
Optimization of Deep Neural Networks Using SoCs with OpenCL.
Sensors
Rafael Gadea Gironés, Ricardo José Colom-Palero, Vicente Herrero-Bosch
2015 J jnl
Evolutionary optimization of neural networks with heterogeneous computation: study and implementation.
J. Supercomput.
Jorge D. Fe, Ramón José Aliaga, Rafael Gadea Gironés
2013 — conf
Experimental Platform for Accelerate the Training of ANNs with Genetic Algorithm and Embedded System on FPGA.
IWINAC (2)
Jorge D. Fe, Ramón José Aliaga, Rafael Gadea Gironés
2011 J jnl
Octree-based, GPU implementation of a continuous cellular automaton for the simulation of complex, evolving surfaces.
Comput. Phys. Commun.
Néstor Ferrando, M. A. Gosálvez, Joaquín Cerdá, Rafael Gadea Gironés, Kazuo Sato
2010 J jnl
Approximate k-NN delta test minimization method using genetic algorithms: Application to time series.
Neurocomputing
Fernando Mateo, Dusan Sovilj, Rafael Gadea Gironés
2009 — ch.
A 2D Positioning Application in PET Using ANNs.
Encyclopedia of Artificial Intelligence
Fernando Mateo, Ramón José Aliaga, Jorge Daniel Martínez, José María Monzó, Rafael Gadea Gironés
2009 — conf
A mixed hardware-software approach to flexible Artificial Neural Network training on FPGA.
ICSAMOS
Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá, Néstor Ferrando, Vicente Herrero-Bosch
2009 — conf
RCGA-S/RCGA-SP Methods to Minimize the Delta Test for Regression Tasks.
IWANN (1)
Fernando Mateo, Dusan Sovilj, Rafael Gadea Gironés, Amaury Lendasse
2008 J jnl
A Mixed Hardware/Software SOFM Training System.
Computación y Sistemas
Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero, Javier Díaz-Carmona
2008 J jnl
A hardware design of a massive-parallel, modular NN-based vector quantizer for real-time video coding.
Microprocess. Microsystems
Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero
2008 C conf
SoC-Based Implementation of the Backpropagation Algorithm for MLP.
HIS
Ramón José Aliaga, Rafael Gadea Gironés, Ricardo José Colom-Palero, José María Monzó, Christoph W. Lerche, Jorge Daniel Martínez, Angel Sebastiá, Fernando Mateo
2007 J jnl
A wavelet-VQ system for real-time video compression.
J. Real Time Image Process.
Agustín Ramírez-Agundis, Rafael Gadea Gironés, Ricardo José Colom-Palero, Javier Díaz-Carmona
2007 Misc conf
Incidence Position Estimation in a PET Detector Using a Discretized Positioning Circuit and Neural Networks.
IWANN
Fernando Mateo, Ramón José Aliaga, Jorge Daniel Martínez, José María Monzó, Rafael Gadea Gironés
2006 J jnl
A Novel FPGA Architecture of a 2-D Wavelet Transform.
J. VLSI Signal Process.
Ricardo José Colom-Palero, Rafael Gadea Gironés, Angel Sebastià-Cortés
2006 J jnl
An active methodology for teaching electronic systems design.
IEEE Trans. Educ.
Joaquín Cerdá-Boluda, Marcos Martínez Peiró, Miguel A. Larrea Torres, Rafael Gadea Gironés, Ricardo José Colom-Palero
2005 — conf
A Tool for Implementing and Exploring SBM Models: Universal 1D Invertible Cellular Automata.
IWINAC (1)
Joaquín Cerdá, Rafael Gadea Gironés, Jorge Daniel Martínez, Angel Sebastiá
2005 J jnl
FPGA Implementation of a Pipelined On-Line Backpropagation.
J. VLSI Signal Process.
Rafael Gadea Gironés, Ricardo José Colom-Palero, Joaquín Cerdá-Boluda, Angel Sebastià-Cortés
2004 B conf
FPGA Custom DSP for ECG Signal Analysis and Compression.
FPL
Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, José Belenguer
2004 — conf
FPGA Implementations of the RNR Cellular Automata to Model Electrostatic Field.
VECPAR
Joaquín Cerdá-Boluda, Oscar Amoraga-Lechiguero, Ruben Torres-Curado, Rafael Gadea Gironés, Angel Sebastià-Cortés
2004 J jnl
Flexible architecture for the implementation of the two-dimensional discrete wavelet transform (2D-DWT) oriented to FPGA devices.
Microprocess. Microsystems
Ricardo José Colom-Palero, Rafael Gadea Gironés, Francisco José Ballester-Merelo, Marcos Martínez Peiró
2003 B conf
FPGA Implementation of Adaptive Non-linear Predictors for Video Compression.
FPL
Rafael Gadea Gironés, Agustín Ramírez-Agundis, Joaquín Cerdá-Boluda, Ricardo José Colom-Palero
2003 — conf
Implementing a Margolus Neighborhood Cellular Automata on a FPGA.
IWANN (2)
Joaquín Cerdá, Rafael Gadea Gironés, Guillermo Payá Vayá
2003 B conf
On the Implementation of a Margolus Neighborhood Cellular Automata on FPGA.
FPL
Joaquín Cerdá, Rafael Gadea Gironés, Vicente Herrero-Bosch, Angel Sebastiá
2000 — conf
Artificial Neural Network Implementation on a Single FPGA of a Pipelined On-Line Backpropagation.
ISSS
Rafael Gadea Gironés, Joaquín Cerdá, Francisco José Ballester-Merelo, Antonio Mocholí Salcedo
2000 B conf
The Role of the Embedded Memories in the Implementation of Artificial Neural Networks.
FPL
Rafael Gadea Gironés, Vicente Herrero-Bosch, Angel Sebastiá, Antonio Mocholí Salcedo
1999 — conf
Forward-Backward Parallelism in On-Line Backpropagation.
IWANN (2)
Rafael Gadea Gironés, Antonio Mocholí Salcedo
1999 — conf
Implementation with FPGAs of a pipelined on-line backpropagation.
ICECS
Rafael Gadea Gironés, Antonio Mocholí Salcedo