Rafael Castro-López

94 papers A 7B 2C 9Journal 26Unranked 50
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Comprehensive Approach to Improving the Thermal Reliability of RTN-Based PUFs.
IEEE Trans. Circuits Syst. I Regul. Pap.
F. de Los Santos-Prieto, F. J. Rubio-Barbero, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2025 C conf
A Ring-Oscillator-based Odometer to Unveil the Actual IC Usage Time.
ISCAS
F. de Los Santos-Prieto, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, F. V. Fernandez
2025 — conf
Towards a Reliable PUF Using Organic Thin-Film Transistors.
SMACD
F. de Los Santos-Prieto, Deborah Eric, Marc Porti, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Montserrat Nafría
2025 — conf
When Variability Meets Security.
IRPS
Rafael Castro-López, Javier Diaz-Fortuny, Elisenda Roca, Francisco V. Fernández
2025 J jnl
Workload Compression Techniques to Scale Defect-Centric BTI Models to the Circuit Level.
IEEE Trans. Circuits Syst. I Regul. Pap.
Andrés Santana-Andreo, Victor M. van Santen, Rafael Castro-López, Elisenda Roca, Hussam Amrouch, Francisco V. Fernández
2024 — conf
Harvesting RTN for True Random Number Generators and Physical Unclonable Functions.
SMACD
F. J. Rubio-Barbero, F. de Los Santos-Prieto, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2024 — conf
Optimization-based bit selection technique to improve the reliability of PUFs.
SMACD
F. de Los Santos-Prieto, F. J. Rubio-Barbero, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2024 — conf
Streamlined design methodology for Cell-Based DCOs.
SMACD
Andrés Santana-Andreo, Jose M. Gata-Romero, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2024 — conf
Towards a Digital Twin of a Time-Dependent Variability Characterization Laboratory.
SMACD
Jose M. Gata-Romero, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2023 — conf
A Peak Detect & Hold circuit to measure and exploit RTN in a 65-nm CMOS PUF.
SMACD
F. J. Rubio-Barbero, Eros Camacho-Ruiz, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2023 — conf
A Test Module for Aging Characterization of Digital Circuits.
SMACD
Jose M. Gata-Romero, Andrés Santana-Andreo, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2023 — conf
A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array.
SMACD
Andrés Santana-Andreo, Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2023 — conf
Challenges and solutions to the defect-centric modeling and circuit simulation of time-dependent variability.
IRPS
Javier Martín-Martínez, Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Montserrat Nafría
2023 — conf
Characterizing BTI and HCD in 1.2V 65nm CMOS Oscillators made from Combinational Standard Cells and Processor Logic Paths.
IRPS
Victor M. van Santen, Jose M. Gata-Romero, Juan Núñez, Rafael Castro-López, Elisenda Roca, Hussam Amrouch
2023 — conf
Design considerations for a CMOS 65-nm RTN-based PUF.
SMACD
Eros Camacho-Ruiz, F. J. Rubio-Barbero, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2023 — conf
Reliability evaluation of IC Ring Oscillator PUFs.
SMACD
Jose M. Gata-Romero, Elisenda Roca, Juan Núñez, Rafael Castro-López, Francisco V. Fernández
2023 — conf
Strategies for parameter extraction of the time constant distribution of time-dependent variability models for nanometer-scale devices.
SMACD
Francisco V. Fernández, Elisenda Roca, Pablo Saraza-Canflanca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López
2022 J jnl
A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs.
Integr.
Andrés Santana-Andreo, Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Piedad Brox, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2022 — conf
A Smart SRAM-Cell Array for the Experimental Study of Variability Phenomena in CMOS Technologies.
IRPS
Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Andrés Santana-Andreo, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2022 C conf
A novel Physical Unclonable Function using RTN.
ISCAS
Eros Camacho-Ruiz, Rafael Castro-López, Elisenda Roca, Piedad Brox, Francisco V. Fernández
2022 — conf
A systematic approach to RTN parameter fitting based on the Maximum Current Fluctuation.
SMACD
Pablo Saraza-Canflanca, Javier Martín-Martínez, Elisenda Roca, Rafael Castro-López, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2022 — conf
Characterization and analysis of BTI and HCI effects in CMOS current mirrors.
SMACD
Andrés Santana-Andreo, Pablo Martín-Lloret, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2022 — conf
High-level design of a novel PUF based on RTN.
SMACD
Eros Camacho-Ruiz, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2022 — conf
Impact of BTI and HCI on the reliability of a Majority Voter.
SMACD
Andrés Santana-Andreo, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2022 — conf
Machine Learning Approaches for Transformer Modeling.
SMACD
Fábio Passos, Nuno C. Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2022 J jnl
On the Impact of the Biasing History on the Characterization of Random Telegraph Noise.
IEEE Trans. Instrum. Meas.
Pablo Saraza-Canflanca, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2022 — conf
On the use of an RTN simulator to explore the quality trade-offs of a novel RTN-based PUF.
SMACD
Eros Camacho-Ruiz, Andrés Santana-Andreo, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2021 J jnl
Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs.
IEEE Access
António Canelas, Fábio Passos, Nuno Lourenço, Ricardo Martins, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2020 J jnl
A Multilevel Bottom-Up Optimization Methodology for the Automated Synthesis of RF Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fábio Passos, Elisenda Roca, Javier J. Sieiro, Rafaella Fiorelli, Rafael Castro-López, José María López-Villegas, Francisco V. Fernández
2020 J jnl
A robust and automated methodology for the analysis of Time-Dependent Variability at transistor level.
Integr.
Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2020 J jnl
Flexible Setup for the Measurement of CMOS Time-Dependent Variability With Array-Based Integrated Circuits.
IEEE Trans. Instrum. Meas.
Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Francisco V. Fernández, Montserrat Nafría
2020 — conf
Improving the reliability of SRAM-based PUFs in the presence of aging.
DTIS
Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Piedad Brox, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2020 J jnl
Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology.
IEEE Access
Fábio Passos, Elisenda Roca, Ricardo Martins, Nuno Lourenço, Saiyd Ahyoune, Javier J. Sieiro, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2020 J jnl
Synthesis of mm-Wave Wideband Receivers in 28-nm CMOS Technology for Automotive Radar Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fábio Passos, Miguel Chanca, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2019 — conf
A New Time Efficient Methodology for the Massive Characterization of RTN in CMOS Devices.
IRPS
G. Pedreira, Javier Martín-Martínez, Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Montserrat Nafría
2019 J jnl
A Versatile CMOS Transistor Array IC for the Statistical Characterization of Time-Zero Variability, RTN, BTI, and HCI.
IEEE J. Solid State Circuits
Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Xavier Aragonès, Enrique Barajas, Diego Mateo, Francisco V. Fernández, Montserrat Nafría
2019 J jnl
A two-step surrogate modeling strategy for single-objective and multi-objective optimization of radiofrequency circuits.
Soft Comput.
Fábio Passos, Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2019 — conf
An IC Array for the Statistical Characterization of Time-Dependent Variability of Basic Circuit Blocks.
SMACD
Pablo Martín-Lloret, Juan Núñez, Elisenda Roca, Rafael Castro-López, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019 — conf
Experimental Characterization of Time-Dependent Variability in Ring Oscillators.
SMACD
Juan Núñez, Elisenda Roca, Rafael Castro-López, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019 A conf
Generation of Lifetime-Aware Pareto-Optimal Fronts Using a Stochastic Reliability Simulator.
DATE
Antonio Toro-Frías, Pablo Saraza-Canflanca, Fábio Passos, Pablo Martín-Lloret, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019 A conf
New method for the automated massive characterization of Bias Temperature Instability in CMOS transistors.
DATE
Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca Moreno, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019 — conf
Synthesis of mm-Wave circuits using-EM-simulated passive structure libraries.
SMACD
Fábio Passos, Elisenda Roca, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2019 — conf
TiDeVa: A Toolbox for the Automated and Robust Analysis of Time-Dependent Variability at Transistor Level.
SMACD
Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2019 J jnl
Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Povoa, António Canelas, Elisenda Roca, Rafael Castro-López, Javier J. Sieiro, Francisco V. Fernández, Nuno Horta
2018 J jnl
A Comparison of Automated RF Circuit Design Methodologies: Online Versus Offline Passive Component Design.
IEEE Trans. Very Large Scale Integr. Syst.
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2018 — conf
A Model Parameter Extraction Methodology Including Time-Dependent Variability for Circuit Reliability Simulation.
SMACD
Javier Diaz-Fortuny, Pablo Saraza-Canflanca, Antonio Toro-Frías, Rafael Castro-López, Javier Martín-Martínez, Elisenda Roca, Rosana Rodríguez, Francisco V. Fernández, Montserrat Nafría
2018 — conf
Analysis of Body Bias and RTN-Induced Frequency Shift of Low Voltage Ring Oscillators in FDSOI Technology.
PATMOS
Enrique Barajas, Xavier Aragonès, Diego Mateo, Francesc Moll, Antonio Rubio, Javier Martín-Martínez, Rosana Rodríguez, Marc Porti, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2018 — conf
Automated Massive RTN Characterization Using a Transistor Array Chip.
SMACD
Pablo Saraza-Canflanca, Javier Diaz-Fortuny, Antonio Toro-Frías, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2018 C conf
CMOS Characterization and Compact Modelling for Circuit Reliability Simulation.
IOLTS
Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2018 — conf
Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models.
SMACD
Pablo Saraza-Canflanca, D. Malagon, Fábio Passos, A. Toro, Juan Núñez, Javier Diaz-Fortuny, Rafael Castro-López, Elisenda Roca, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2018 J jnl
Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology.
Integr.
Fábio Passos, Ricardo Martins, Nuno Lourenço, Elisenda Roca, Ricardo Povoa, António Canelas, Rafael Castro-López, Nuno Horta, Francisco V. Fernández
2018 — conf
Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs.
SMACD
Fábio Passos, Ricardo Martins, Nuno C. Lourenço, Elisenda Roca, Rafael Castro-López, Ricardo Povoa, António Canelas, Nuno Horta, Francisco V. Fernández
2018 — conf
Lifetime Calculation Using a Stochastic Reliability Simulator for Analog ICs.
SMACD
Antonio Toro-Frías, Pablo Martín-Lloret, Javier Martín-Martínez, Rafael Castro-López, Elisenda Roca, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2018 — conf
Weighted time lag plot defect parameter extraction and GPU-based BTI modeling for BTI variability.
IRPS
Victor M. van Santen, Javier Diaz-Fortuny, Hussam Amrouch, Javier Martín-Martínez, Rosana Rodríguez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Jörg Henkel, Montserrat Nafría
2017 C conf
A size-adaptive time-step algorithm for accurate simulation of aging in analog ICs.
ISCAS
Pablo Martín-Lloret, Antonio Toro-Frías, Javier Martín-Martínez, Rafael Castro-López, Elisenda Roca, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2017 — conf
A transistor array chip for the statistical characterization of process variability, RTN and BTI/CHC aging.
SMACD
Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Enrique Barajas, Xavier Aragonès, Diego Mateo
2017 J jnl
An Automated Design Methodology of RF Circuits by Using Pareto-Optimal Fronts of EM-Simulated Inductors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Javier J. Sieiro, José María López-Villegas, Neus Vidal
2017 B conf
An algorithm for a class of real-life multi-objective optimization problems with a sweeping objective.
CEC
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2017 J jnl
An inductor modeling and optimization toolbox for RF circuit design.
Integr.
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2017 — conf
CASE: A reliability simulation tool for analog ICs.
SMACD
Pablo Martín-Lloret, Antonio Toro-Frías, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría
2017 — conf
Including a stochastic model of aging in a reliability simulation flow.
SMACD
Antonio Toro-Frías, Pablo Martín-Lloret, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría
2017 — conf
Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks.
SMACD
Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2017 — conf
New mapping strategies for pre-optimized inductor sets in bottom-up RF IC sizing optimization.
SMACD
Nuno C. Lourenço, Ricardo Martins, Ricardo Povoa, António Canelas, Nuno Horta, Fábio Passos, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2017 J jnl
Radio-frequency inductor synthesis using evolutionary computation and Gaussian-process surrogate modeling.
Appl. Soft Comput.
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2017 — conf
Systematic design of a voltage controlled oscillator using a layout-aware approach.
SMACD
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Ricardo Martins, Nuno C. Lourenço, Ricardo Povoa, António Canelas, Nuno C. G. Horta
2017 — conf
TARS: A toolbox for statistical reliability modeling of CMOS devices.
SMACD
Javier Diaz-Fortuny, Javier Martín-Martínez, Rosana Rodríguez, Montserrat Nafría, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2016 A conf
Accurate synthesis of integrated RF passive components using surrogate models.
DATE
Fábio Passos, Reinier Gonzalez-Echevarria, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2016 — conf
Frequency-dependent parameterized macromodeling of integrated inductors.
SMACD
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández, Y. Ye, Domenico Spina, Tom Dhaene
2016 C conf
High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms.
ISCAS
Manuel Velasco-Jimenez, Rafael Castro-López, José M. de la Rosa
2016 C conf
Live demonstration: High-level optimization of ΣΔ modulators using multi-objetive evolutionary algorithms.
ISCAS
Manuel Velasco-Jimenez, Rafael Castro-López, José M. de la Rosa
2016 J jnl
Reliability simulation for analog ICs: Goals, solutions, and challenges.
Integr.
Antonio Toro-Frías, Pablo Martín-Lloret, Javier Martín-Martínez, Rafael Castro-López, Elisenda Roca, Rosana Rodríguez, Montserrat Nafría, Francisco V. Fernández
2016 — conf
SIDe-O: A toolbox for surrogate inductor design and optimization.
SMACD
Fábio Passos, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2015 C conf
Design space exploration using hierarchical composition of performance models.
ISCAS
Manuel Velasco-Jimenez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2015 C conf
Physical vs. surrogate models of passive RF devices.
ISCAS
Fábio Passos, Mouna Kotti, Reinier Gonzalez-Echevarria, M. Helena Fino, Mourad Fakhfakh, Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2014 J jnl
Automated Generation of the Optimal Performance Trade-Offs of Integrated Inductors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Reinier Gonzalez-Echevarria, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Javier J. Sieiro, Neus Vidal, José María López-Villegas
2014 A conf
Implementation issues in the hierarchical composition of performance models of analog circuits.
DATE
Manuel Velasco-Jimenez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2011 — conf
Layout-aware Pareto fronts of electronic circuits.
ECCTD
Antonio Toro-Frías, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández
2010 J jnl
A 0.13 µm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications.
Microelectron. J.
Alonso Morgado, Rocío del Río Fernández, José M. de la Rosa, Rafael Castro-López, Maria Belen Pérez-Verdú
2010 B conf
Stopping criteria in evolutionary algorithms for multi-objective performance optimization of integrated inductors.
IEEE Congress on Evolutionary Computation
Francisco V. Fernández, Juan Esteban-Muller, Elisenda Roca, Rafael Castro-López
2009 J jnl
A memetic approach to the automatic design of high-performance analog integrated circuits.
ACM Trans. Design Autom. Electr. Syst.
Bo Liu, Francisco V. Fernández, Georges G. E. Gielen, Rafael Castro-López, Elisenda Roca
2009 J jnl
AMS/RF-CMOS circuit design for wireless transceivers.
Integr.
Rafael Castro-López, Delia Rodríguez de Llera, Mohammed Ismail, Francisco V. Fernández
2009 J jnl
Adaptive CMOS analog circuits for 4G mobile terminals - Review and state-of-the-art survey.
Microelectron. J.
José M. de la Rosa, Rafael Castro-López, Alonso Morgado, Edwin C. Becerra-Alvarez, Rocío del Río, Francisco V. Fernández, Maria Belen Pérez-Verdú
2009 A conf
Analog layout synthesis - Recent advances in topological approaches.
DATE
Helmut Gräb, Florin Balasa, Rafael Castro-López, Yu-Wei Chang, Francisco V. Fernández, Mark Po-Hung Lin, Martin Strasser
2009 — conf
Applications of evolutionary computation techniques to analog, mixed-signal and RF circuit design - an overview.
ICECS
Elisenda Roca, Mourad Fakhfakh, Rafael Castro-López, Francisco V. Fernández
2009 — conf
Hierarchical synthesis based on pareto-optimal fronts.
ECCTD
Elisenda Roca, Rafael Castro-López, Francisco V. Fernández
2008 J jnl
An Integrated Layout-Synthesis Approach for Analog ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Rafael Castro-López, Oscar Guerra, Elisenda Roca, Francisco V. Fernández
2008 J jnl
Behavioral modeling, simulation and synthesis of multi-standard wireless receivers in MATLAB/SIMULINK.
Integr.
Alonso Morgado, V. J. Rivas, Rocío del Río, Rafael Castro-López, Francisco V. Fernández, José M. de la Rosa
2006 — conf
A 12-bit CMOS Current Steering D/A Converter for Embedded Systems.
APCCAS
Jesús Ruiz-Amaya, Manuel Delgado-Restituto, Juan Francisco Fernández-Bootello, Davide Brandano, Rafael Castro-López, José M. de la Rosa
2003 — conf
A 1000FPS@128×128 vision processor with 8-bit digitized I/O.
ESSCIRC
Gustavo Liñán Cembrano, Ángel Rodríguez-Vázquez, Rafael Castro-López, Servando Espejo-Meana
2003 — conf
Accurate VHDL-based simulation of Sigma-Delta modulators.
ISCAS (4)
Rafael Castro-López, Francisco V. Fernández, Fernando Medeiro, Ángel Rodríguez-Vázquez
2003 A conf
Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages.
DATE
Rafael Castro-López, Francisco V. Fernández, Fernando Medeiro, Ángel Rodríguez-Vázquez
2003 C conf
Description Languages and Tools for the Behavioural Simulation of SD Modulators: a Comparative Survey.
FDL
Rafael Castro-López, José M. de la Rosa, R. Romay, Rocío del Río, Fernando Medeiro, Francisco V. Fernández
2001 A conf
Retargeting of mixed-signal blocks for SoCs.
DATE
Rafael Castro-López, Francisco V. Fernández, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez
1999 — conf
RAPID-retargetability for reusability of application-driven quadrature D/A interface block design.
ICECS
José E. Franca, Nuno Horta, M. Pereira, João C. Vital, Rafael Castro-López, Manuel Delgado-Restituto, Francisco V. Fernández, Ángel Rodríguez-Vázquez, J. Ramos, P. Santos