Radu Teodorescu

55 papers A* 17A 2B 7C 3Misc 4Journal 15Unranked 7

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	MicroSampler: A Framework for Microarchitecture-Level Leakage Detection in Constant Time Execution. DSN Moein Ghaniyoun, Kristin Barber, Yinqian Zhang, Radu Teodorescu
2024	—	`conf`	Voltage Noise-Based Adversarial Attacks on Machine Learning Inference in Multi-Tenant FPGA Accelerators. HOST Saikat Majumdar, Radu Teodorescu
2023	A*	`conf`	TEESec: Pre-Silicon Vulnerability Discovery for Trusted Execution Environments. ISCA Moein Ghaniyoun, Kristin Barber, Yuan Xiao, Yinqian Zhang, Radu Teodorescu
2022	J	`jnl`	A Pre-Silicon Approach to Discovering Microarchitectural Vulnerabilities in Security Critical Applications. IEEE Comput. Archit. Lett. Kristin Barber, Moein Ghaniyoun, Yinqian Zhang, Radu Teodorescu
2022	A*	`conf`	A Systematic Look at Ciphertext Side Channels on AMD SEV-SNP. SP Mengyuan Li, Luca Wilke, Jan Wichelmann, Thomas Eisenbarth, Radu Teodorescu, Yinqian Zhang
2022	—	`conf`	Characterizing Side-Channel Leakage of DNN Classifiers though Performance Counters. HOST Saikat Majumdar, Mohammad Hossein Samavatian, Radu Teodorescu
2022	J	`jnl`	DNNShield: Dynamic Randomized Model Sparsification, A Defense Against Adversarial Machine Learning. CoRR Mohammad Hossein Samavatian, Saikat Majumdar, Kristin Barber, Radu Teodorescu
2022	—	`conf`	ENCLYZER: Automated Analysis of Transient Data Leaks on Intel SGX. SEED Jiuqin Zhou, Yuan Xiao, Radu Teodorescu, Yinqian Zhang
2022	J	`jnl`	Special Issue on Top Picks From the 2021 Computer Architecture Conferences. IEEE Micro Sudhanva Gurumurthi, Radu Teodorescu
2021	Misc	`conf`	A Fused Inference Design for Pattern-Based Sparse CNN on Edge Devices. HiPC Jia Guo, Radu Teodorescu, Gagan Agrawal
2021	B	`conf`	Fused DSConv: Optimizing Sparse CNN Inference for Execution on Edge Devices. CCGRID Jia Guo, Radu Teodorescu, Gagan Agrawal
2021	J	`jnl`	HASI: Hardware-Accelerated Stochastic Inference, A Defense Against Adversarial Machine Learning Attacks. CoRR Mohammad Hossein Samavatian, Saikat Majumdar, Kristin Barber, Radu Teodorescu
2021	A*	`conf`	INTROSPECTRE: A Pre-Silicon Framework for Discovery and Analysis of Transient Execution Vulnerabilities. ISCA Moein Ghaniyoun, Kristin Barber, Yinqian Zhang, Radu Teodorescu
2021	J	`jnl`	Using Undervolting as an On-Device Defense Against Adversarial Machine Learning Attacks. CoRR Saikat Majumdar, Mohammad Hossein Samavatian, Kristin Barber, Radu Teodorescu
2021	—	`conf`	Using Undervolting as an on-Device Defense Against Adversarial Machine Learning Attacks. HOST Saikat Majumdar, Mohammad Hossein Samavatian, Kristin Barber, Radu Teodorescu
2020	B	`conf`	A Pattern-Based API for Mapping Applications to a Hierarchy of Multi-Core Devices. CCGRID Jia Guo, Radu Teodorescu, Gagan Agrawal
2020	J	`jnl`	RNNFast: An Accelerator for Recurrent Neural Networks Using Domain-Wall Memory. ACM J. Emerg. Technol. Comput. Syst. Mohammad Hossein Samavatian, Anys Bacha, Li Zhou, Radu Teodorescu
2020	A*	`conf`	SPEECHMINER: A Framework for Investigating and Measuring Speculative Execution Vulnerabilities. NDSS Yuan Xiao, Yinqian Zhang, Radu Teodorescu
2019	—	`conf`	Accident Risk Prediction based on Heterogeneous Sparse Data: New Dataset and Insights. SIGSPATIAL/GIS Sobhan Moosavi, Mohammad Hossein Samavatian, Srinivasan Parthasarathy, Radu Teodorescu, Rajiv Ramnath
2019	J	`jnl`	Accident Risk Prediction based on Heterogeneous Sparse Data: New Dataset and Insights. CoRR Sobhan Moosavi, Mohammad Hossein Samavatian, Srinivasan Parthasarathy, Radu Teodorescu, Rajiv Ramnath
2019	Misc	`conf`	Adaptive parallel execution of deep neural networks on heterogeneous edge devices. SEC Li Zhou, Mohammad Hossein Samavatian, Anys Bacha, Saikat Majumdar, Radu Teodorescu
2019	—	`conf`	Distributing Deep Neural Networks with Containerized Partitions at the Edge. HotEdge Li Zhou, Hao Wen, Radu Teodorescu, David H. C. Du
2019	J	`jnl`	Isolating Speculative Data to Prevent Transient Execution Attacks. IEEE Comput. Archit. Lett. Kristin Barber, Anys Bacha, Li Zhou, Yinqian Zhang, Radu Teodorescu
2019	J	`jnl`	SPEECHMINER: A Framework for Investigating and Measuring Speculative Execution Vulnerabilities. CoRR Yuan Xiao, Yinqian Zhang, Radu Teodorescu
2019	B	`conf`	SpecShield: Shielding Speculative Data from Microarchitectural Covert Channels. PACT Kristin Barber, Anys Bacha, Li Zhou, Yinqian Zhang, Radu Teodorescu
2018	B	`conf`	C-Graph: A Highly Efficient Concurrent Graph Reachability Query Framework. ICPP Li Zhou, Ren Chen, Yinglong Xia, Radu Teodorescu
2018	C	`conf`	NVCool: When Non-Volatile Caches Meet Cold Boot Attacks. ICCD Xiang Pan, Anys Bacha, Spencer Rudolph, Li Zhou, Yinqian Zhang, Radu Teodorescu
2018	J	`jnl`	RNNFast: An Accelerator for Recurrent Neural Networks Using Domain Wall Memory. CoRR Mohammad Hossein Samavatian, Anys Bacha, Li Zhou, Radu Teodorescu
2017	A	`conf`	Respin: Rethinking Near-Threshold Multiprocessor Design with Non-volatile Memory. IPDPS Xiang Pan, Anys Bacha, Radu Teodorescu
2016	A*	`conf`	Core tunneling: Variation-aware voltage noise mitigation in GPUs. HPCA Renji Thomas, Kristin Barber, Naser Sedaghati, Li Zhou, Radu Teodorescu
2016	B	`conf`	EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures. ISPASS Renji Thomas, Naser Sedaghati, Radu Teodorescu
2016	A*	`conf`	One Bit Flips, One Cloud Flops: Cross-VM Row Hammer Attacks and Privilege Escalation. USENIX Security Symposium Yuan Xiao, Xiaokuan Zhang, Yinqian Zhang, Radu Teodorescu
2016	A*	`conf`	Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks. MICRO Dimitrios Skarlatos, Renji Thomas, Aditya Agrawal, Shibin Qin, Robert C. N. Pilawa-Podgurski, Ulya R. Karpuzcu, Radu Teodorescu, Nam Sung Kim, Josep Torrellas
2015	A*	`conf`	Authenticache: harnessing cache ECC for system authentication. MICRO Anys Bacha, Radu Teodorescu
2015	J	`jnl`	Commentary: When the brain takes a break: a model-based analysis of mind wandering. Frontiers Comput. Neurosci. Vadim Axelrod, Radu Teodorescu
2014	C	`conf`	NVSleep: Using non-volatile memory to enable fast sleep/wakeup of idle cores. ICCD Xiang Pan, Radu Teodorescu
2014	J	`jnl`	On Using the Roofline Model with Lower Bounds on Data Movement. ACM Trans. Archit. Code Optim. Venmugil Elango, Naser Sedaghati, Fabrice Rastello, Louis-Noël Pouchet, J. Ramanujam, Radu Teodorescu, P. Sadayappan
2014	A*	`conf`	Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors. MICRO Anys Bacha, Radu Teodorescu
2014	B	`conf`	Using STT-RAM to enable energy-efficient near-threshold chip multiprocessors. PACT Xiang Pan, Radu Teodorescu
2013	A*	`conf`	Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors. ISCA Anys Bacha, Radu Teodorescu
2013	J	`jnl`	Runtime failure rate targeting for energy-efficient reliability in chip microprocessors. Concurr. Comput. Pract. Exp. Timothy N. Miller, Nagarjuna Surapaneni, Radu Teodorescu
2012	A*	`conf`	Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips. HPCA Timothy N. Miller, Xiang Pan, Renji Thomas, Naser Sedaghati, Radu Teodorescu
2012	J	`jnl`	Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units. IEEE Comput. Archit. Lett. Timothy N. Miller, Renji Thomas, Radu Teodorescu
2012	A*	`conf`	VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors. ISCA Timothy N. Miller, Renji Thomas, Xiang Pan, Radu Teodorescu
2011	B	`conf`	StVEC: A Vector Instruction Extension for High Performance Stencil Computation. PACT Naser Sedaghati, Renji Thomas, Louis-Noël Pouchet, Radu Teodorescu, P. Sadayappan
2010	C	`conf`	Flexible Error Protection for Energy Efficient Reliable Architectures. SBAC-PAD Timothy N. Miller, Nagarjuna Surapaneni, Radu Teodorescu
2010	A*	`conf`	Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches. MICRO Timothy N. Miller, Renji Thomas, James Dinan, Bruce M. Adcock, Radu Teodorescu
2008	A*	`conf`	Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. ISCA Radu Teodorescu, Josep Torrellas
2007	A*	`conf`	HARD: Hardware-Assisted Lockset-based Race Detection. HPCA Pin Zhou, Radu Teodorescu, Yuanyuan Zhou
2007	A*	`conf`	Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. MICRO Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas
2006	—	`conf`	Log-based architectures for general-purpose monitoring of deployed code. ASID Shimin Chen, Babak Falsafi, Phillip B. Gibbons, Michael Kozuch, Todd C. Mowry, Radu Teodorescu, Anastassia Ailamaki, Limor Fix, Gregory R. Ganger, Bin Lin, Steven W. Schlosser
2006	J	`jnl`	SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback. IEEE Micro Radu Teodorescu, Jun Nakano, Josep Torrellas
2005	Misc	`conf`	Prototyping Architectural Support for Program Rollback Using FPGAs. FCCM Radu Teodorescu, Josep Torrellas
2004	A*	`conf`	Using code collection to support large applications on mobile devices. MobiCom Lucian Popa, Irina Athanasiu, Costin Raiciu, Raju Pandey, Radu Teodorescu
2001	Misc	`conf`	Using JIT Compilation and Configurable Runtime Systems for Efficient Deployment of Java Programs on Ubiquitous Devices. UbiComp Radu Teodorescu, Raju Pandey