Rabindra K. Roy

42 papers A* 2A 6C 2Misc 12Journal 15Unranked 4
YearRankTypeTitle / Venue / Authors
2000 J jnl
EDA challenges facing future microprocessor design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
T. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra K. Roy, Gregory S. Spirakis, Naveed A. Sherwani, Craig Peterson
1999 Misc conf
Characterizing Individual Gate Power Sensitivity in Low Power Design.
VLSI Design
Unni Narayanan, Georgios I. Stamoulis, Rabindra K. Roy
1999 J jnl
Partial Reset Methodology and Experiments for Improving Random-Pattern Testability and BIST of Sequential Circuits.
J. Electron. Test.
Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee
1998 J jnl
Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis.
J. VLSI Signal Process.
Huy T. Nguyen, Abhijit Chatterjee, Rabindra K. Roy
1998 — conf
Considering Testability during High-level Design (Embedded Tutorial).
ASP-DAC
Sujit Dey, Anand Raghunathan, Rabindra K. Roy
1998 J jnl
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.
J. Electron. Test.
Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
1998 Misc conf
Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.
VLSI Design
Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey
1998 Misc conf
Partial Reset Methodologies for Improving Random-Pattern Testability and BIST of Sequential Circuits.
VLSI Design
Huy Nguyen, Rabindra K. Roy, Abhijit Chatterjee
1997 J jnl
Concurrent Error Detection in Nonlinear Digital Circuits Using Time-Freeze Linearization.
IEEE Trans. Computers
Abhijit Chatterjee, Rabindra K. Roy
1997 Misc conf
Impact of Partial Reset on Fault Independent Testing and BIST.
VLSI Design
Huy Nguyen, Abhijit Chatterjee, Rabindra K. Roy
1997 Misc conf
T5: Low-Power Design.
VLSI Design
Kaushik Roy, Rabindra K. Roy, Ramesh Harjani, K. S. Murthy
1996 J jnl
Initialization issues in asynchronous circuit synthesis.
J. Electron. Test.
Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar
1996 Misc conf
Synchronous Test Generation Model for Asynchronous Circuits.
VLSI Design
Savita Banerjee, Srimat T. Chakradhar, Rabindra K. Roy
1996 J jnl
Synthesis of initializable asynchronous circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
1995 A conf
Advantages of High-Level Test Synthesis over Design for Test.
ITC
Rabindra K. Roy
1995 J jnl
Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
1995 J jnl
Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
1995 J jnl
Guest Editors' Introduction: More Practical Asynchronous Design.
IEEE Des. Test Comput.
Tam-Anh Chu, Rabindra K. Roy
1995 — conf
Synthesis-for-testability using transformations.
ASP-DAC
Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy
1994 — conf
Behavioral synthesis of low-cost partial scan designs for DSP applications.
ICASSP (2)
Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy
1994 Misc conf
Design for diagnosability of linear digital filters using time-space expansion.
VTS
Abhijit Chatterjee, Rabindra K. Roy
1994 J jnl
Guest Editor's Introduction: Practical Asynchronous Design.
IEEE Des. Test Comput.
Tam-Anh Chu, Rabindra K. Roy
1994 C conf
Initialization Isuues in the Synthesis of Asynchronous Circuits.
ICCD
Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
1994 — conf
Signal Transition Graph Transformations for Initializability.
EDAC-ETC-EUROASIC
Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar, Dhiraj K. Pradhan
1994 Misc conf
Synthesis of Initializable Asynchronous Circuits.
VLSI Design
Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan
1994 Misc conf
Synthesis of Low Power Linear DSP Circuits Using Activity Metrics.
VLSI Design
Abhijit Chatterjee, Rabindra K. Roy
1994 Misc conf
Synthesizing designs with low-cardinality minimum feedback vertex set for partial scan application.
VTS
Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy
1993 A* conf
An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition.
DAC
Abhijit Chatterjee, Rabindra K. Roy
1993 C conf
Concurrent Error Detection in Nonlinear Digital Circuits with Applications to Adaptive Filters.
ICCD
Abhijit Chatterjee, Rabindra K. Roy
1993 A conf
Exploiting hardware sharing in high-level synthesis for partial scan optimization.
ICCAD
Sujit Dey, Miodrag Potkonjak, Rabindra K. Roy
1993 Misc conf
Greedy Hardware Optimization for Linear Digital Systems Using Number Splitting.
VLSI Design
Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu
1993 J jnl
Greedy hardware optimization for linear digital circuits using number splitting and refactorization.
IEEE Trans. Very Large Scale Integr. Syst.
Abhijit Chatterjee, Rabindra K. Roy, Manuel A. d'Abreu
1992 A conf
Automatic test generation for linear digital systems with bi-level search using matrix transform methods.
ICCAD
Rabindra K. Roy, Abhijit Chatterjee, Janak H. Patel, Jacob A. Abraham, Manuel A. d'Abreu
1992 Misc conf
Delay fault testing of iterative arithmetic arrays.
VTS
Rabindra K. Roy, Naveena Nagi, Abhijit Chatterjee, Manuel A. d'Abreu
1992 J jnl
Dynamic redundancy identification in automatic test generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Miron Abramovici, David T. Miller, Rabindra K. Roy
1992 J jnl
Test compaction for sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Thomas M. Niermann, Rabindra K. Roy, Janak H. Patel, Jacob A. Abraham
1991 J jnl
Efficient testing strategies for bit- and digit-serial arrays used in digital signal processors.
Digit. Signal Process.
Abhijit Chatterjee, Rabindra K. Roy, Jacob A. Abraham, Janak H. Patel
1991 A conf
The Best Flip-Flops to Scan.
ITC
Miron Abramovici, James J. Kulikowski, Rabindra K. Roy
1990 — —
Timing verification and synthesis of circuits for delay fault testability
Rabindra K. Roy
1989 A conf
Dynamic redundancy identification in automatic test generation.
ICCAD
Miron Abramovici, David T. Miller, Rabindra K. Roy
1988 A conf
Compaction of ATPG-generated test sequences for sequential circuits.
ICCAD
Rabindra K. Roy, Thomas M. Niermann, Janak H. Patel, Jacob A. Abraham, Resve A. Saleh
1988 A* conf
Fault Simulation in a Distributed Environment.
DAC
Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers
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