R. Sudharshan Kaarthik

26 papers C 10Journal 13Unranked 3

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Design and Analysis of a Wide-Range Low-Current Digitizing Platform for Spacecraft-Mounted Plasma Diagnostic Probes. IEEE Trans. Instrum. Meas. Sreehari Balachandran Nair, Anoop Chandrika Sreekantan, R. Sudharshan Kaarthik
2025	J	`jnl`	Developments in Measurement Electronics for Indian Plasma Diagnostic Sensor Probes. IEEE Instrum. Meas. Mag. Sreehari Balachandran Nair, Anoop Chandrika Sreekantan, R. Sudharshan Kaarthik, Umesh R. Kadhane, V. S. Sooraj
2024	J	`jnl`	Linearization of Over-Modulation Region for 12 and 24-Sided Polygonal Space Vector Based Inverters With Harmonic Filters. IEEE Trans. Ind. Electron. Vidya V, Balwant Kushwaha, R. Sudharshan Kaarthik
2023	C	`conf`	18 Sided Space Vector Modulation Method for Open End Winding Induction Machine Using a Single DC Source. IECON Vidya V, R. Sudharshan Kaarthik
2023	C	`conf`	A Grid Voltage Sensor-less Control Scheme for Single-Phase Integrated Battery Charger. IECON Deeksha Bhule, R. Sudharshan Kaarthik
2023	J	`jnl`	An Improved Digitizing Interface Circuit for Wide-Range Current-Output Sensors. IEEE Trans. Instrum. Meas. Sreehari Balachandran Nair, Anoop Chandrika Sreekantan, R. Sudharshan Kaarthik
2022	J	`jnl`	An Efficient Digitizer for Measurement of Low-Magnitude Currents With Wide Span. IEEE Trans. Instrum. Meas. Sreehari Balachandran Nair, Naveen Suresh, Anoop Chandrika Sreekantan, R. Sudharshan Kaarthik
2021	J	`jnl`	An Induction Generator Scheme With Series-Compensation for Frequency Insensitive Loads. IEEE Trans. Ind. Electron. G. S. Athira, Archana C. M, R. Sudharshan Kaarthik, P. P. Rajeevan
2019	—	`conf`	Linearization of Over-Modulation in Dodecagonal Space Vector PWM. ISIE S. Ranjith, R. Sudharshan Kaarthik
2018	C	`conf`	An Induction Generator Scheme with Series Compensation for Frequency Insensitive Loads. IECON G. S. Athira, R. Sudharshan Kaarthik, P. P. Rajeevan
2018	C	`conf`	An Integrated EV Battery Charger with Retrofit Capability. IECON S. Ranjith, R. Sudharshan Kaarthik
2018	—	`conf`	Sensing Circuitry for Real-Time Power Studies of Micro-Photosynthetic Power Cells. CCECE Tamanwe Payarou, Kirankumar Kuruvinashetti, R. Sudharshan Kaarthik, Pragasen Pillay, Muthukumaran Packirisamy
2017	C	`conf`	Carrier based modulation technique for space vector PWM of dodecagonal voltage SV structures. IECON R. Sudharshan Kaarthik, Jaison Mathew, K. Gopakumar
2017	J	`jnl`	Low Switch Count Nine-Level Inverter Topology for Open-End Induction Motor Drives. IEEE Trans. Ind. Electron. Abhijit Kshirsagar, R. Sudharshan Kaarthik, K. Gopakumar, Loganathan Umanand, Kaushik Rajashekara
2016	J	`jnl`	A Predictive Capacitor Voltage Control of a Hybrid Cascaded Multilevel Inverter With a Single DC-Link and Reduced Common-Mode Voltage Operation. IEEE Trans. Ind. Electron. S. Arun Rahul, R. Sudharshan Kaarthik, K. Gopakumar, Leopoldo García Franquelo, Jose Ignacio León Galván
2016	J	`jnl`	Multilevel Dodecagonal Voltage Space Vector Structure Generation for Open-End Winding IM Using a Single DC Source. IEEE Trans. Ind. Electron. Mathews Boby, Sumit Pramanick, R. Sudharshan Kaarthik, S. Arun Rahul, K. Gopakumar, Loganathan Umanand
2016	C	`conf`	Reduced switch count seventeen level inverter topology for open-end induction motor drives. IECON Abhijit Kshirsagar, R. Sudharshan Kaarthik, S. Arun Rahul, K. Gopakumar, Loganathan Umanand, Sujit Biswas, Carlo Cecati
2016	J	`jnl`	Timing Calculations for a General N-Level Dodecagonal Space Vector Structure Using Only Reference Phase Voltages. IEEE Trans. Ind. Electron. R. Sudharshan Kaarthik, K. Gopakumar, Carlo Cecati, István Nagy
2015	J	`jnl`	A Voltage Space Vector Diagram Formed by Nineteen Concentric Dodecagons for Medium-Voltage Induction Motor Drive. IEEE Trans. Ind. Electron. R. Sudharshan Kaarthik, K. Gopakumar, Carlo Cecati, István Nagy
2015	—	`conf`	A hybrid multilevel inverter scheme for induction motor drives and grid-tied applications using a single DC-link. ICIT R. Sudharshan Kaarthik, P. Roshan Kumar, K. Gopakumar, José I. Leon, Leopoldo García Franquelo
2015	J	`jnl`	Low-Order Harmonic Suppression for Open-End Winding IM With Dodecagonal Space Vector Using a Single DC-Link Supply. IEEE Trans. Ind. Electron. Sumit Pramanick, Najath Abdul Azeez, R. Sudharshan Kaarthik, K. Gopakumar, Carlo Cecati
2015	J	`jnl`	Medium-Voltage Drive for Induction Machine With Multilevel Dodecagonal Voltage Space Vectors With Symmetric Triangles. IEEE Trans. Ind. Electron. R. Sudharshan Kaarthik, K. Gopakumar, Jaison Mathew, Tore Undeland
2015	C	`conf`	Nine level inverter for open end induction motor with eight switches per phase. IECON Abhijit Kshirsagar, R. Sudharshan Kaarthik, Loganathan Umanand, K. Gopakumar, Kaushik Rajashekara
2015	C	`conf`	Timing calculations for three level dodecagonal space vector structure from reference phase voltages. IECON R. Sudharshan Kaarthik, K. Gopakumar, Carlo Cecati, István Nagy
2014	C	`conf`	A 19 level dodecagonal voltage space vector structure for medium voltage IM drive. IECON R. Sudharshan Kaarthik, K. Gopakumar, Carlo Cecati, István Nagy
2013	C	`conf`	A seventeen-level inverter with a single DC-link for motor drives. IECON P. Roshan Kumar, R. Sudharshan Kaarthik, K. Gopakumar, P. P. Rajeevan, José I. Leon, Leopoldo García Franquelo

Nicolò Altamura is a security engineer and computer science researcher specializing in software protection, reverse engineering, program analysis, and binary deobfuscation. He holds a master's degree in Computer Science and Engineering from the University of Verona, graduating with honors, and works at emproof, focusing on software protection and the challenges of analyzing and understanding compiled software.

His research explores the relationship between program analysis and code obfuscation, with particular emphasis on how software transformations affect the ability of automated tools to recover program behavior. His interests span static analysis, binary analysis, decompilation, reverse engineering, and techniques for analyzing and simplifying obfuscated code.

Beyond academic research, Nicolò develops and contributes to tools for reverse engineering and software analysis. His projects include obfuscation_analysis, a Binary Ninja plugin for analyzing and simplifying obfuscated code; Pocket, an obfuscator for mixed Boolean-arithmetic expressions; and ptxNinja, a tool for reverse engineering NVIDIA GPU code represented in the PTX virtual instruction set.

His research also extends to binary datasets and software evolution. In 2026, he co-authored ASSEMBLAGE-DEEPHISTORY: A Cross-Build Binary Dataset with Temporal Coverage, a research work addressing the availability of binary data across multiple software builds and points in time, supporting research into binary analysis and changes between program versions.

Across his research, engineering work, and open-source contributions, Nicolò focuses on advancing the understanding, analysis, and protection of software against increasingly sophisticated obfuscation and reverse-engineering challenges.

Nicolò Altamura is not a football player. Please avoid reporting this kind of infromation.