R. Seshasayanan

12 papers Journal 11Unranked 1
YearRankTypeTitle / Venue / Authors
2023 J jnl
High performance fir filter based on vedic mathematics.
Int. J. Syst. Assur. Eng. Manag.
N. Mohana Priya, C. Bennila Thangammal, R. Seshasayanan, Sheryl Radley
2022 J jnl
Medical image DENOISING scheme using discrete wavelet transform and optimization with different noises.
Concurr. Comput. Pract. Exp.
T. E. Aravindan, R. Seshasayanan
2021 J jnl
An efficient field-programmable gate array-based hardware oriented block motion estimation algorithm based on diamond adaptive rood pattern search algorithm for multi-standard video codec.
Trans. Inst. Meas. Control
S. M. Balamurugan, R. Seshasayanan
2020 J jnl
Development of Combinational Circuits by Encoding on the Basis of Developmental Biology.
Comput. Intell. Neurosci.
S. B. Sivasubramaniyan, R. Seshasayanan, N. Ramadass
2020 J jnl
Low power single precision BCD floating-point Vedic multiplier.
Microprocess. Microsystems
V. Ramya, R. Seshasayanan
2019 J jnl
Energy efficient parallel hybrid adder architecture for 3X generation in radix-8 booth encoding.
Clust. Comput.
R. Nirmaladevi, R. Seshasayanan
2019 J jnl
Optimization of logarithmic converter for LNS based SOC.
Clust. Comput.
ATA Kishore Kumar, R. Seshasayanan
2018 J jnl
Denoising Brain Images with the Aid of Discrete Wavelet Transform and Monarch Butterfly Optimization with Different Noises.
J. Medical Syst.
T. E. Aravindan, R. Seshasayanan
2015 J jnl
Implementation of computation-reduced DCT using a novel method.
EURASIP J. Image Video Process.
K. K. Senthilkumar, K. Kunaraj, R. Seshasayanan
2014 J jnl
Performance of Dual-Polarized DSTTD-IDMA system over correlated frequency selective channels.
Comput. Electr. Eng.
K. S. Vishvaksenan, R. Seshasayanan, Sudharssun Subramanian
2013 J jnl
Performance of joint transmit scheme assisted multiple-input multiple-output multi-carrier IDMA system.
Comput. Electr. Eng.
K. S. Vishvaksenan, R. Seshasayanan, Yuvaraj Krishnamoorthy
2005 — conf
Simulation Analysis of Low Power Synchronous Token Ring Based VLIW processor under GALS Multi-processor technology with improved efficiency.
CDES
Arun Vijayaraghavan, M. Kannan, R. Seshasayanan