R. Sakthivel

14 papers Journal 11Unranked 3
YearRankTypeTitle / Venue / Authors
2025 — conf
Multi-Parameter Comparative Study of Selective In-Memory Computing Processor Architectures for Performance Optimization in Accelerated Edge Computing.
ACM Great Lakes Symposium on VLSI
V. Mohith, Shekhar Suman Borah, Prabha Sundaravadivel, R. Sakthivel
2024 J jnl
Generalized Bio-Plausible Neuron Model with Refractoriness, Frequency Adaptation and Dynamic Threshold.
J. Circuits Syst. Comput.
I. Munavar Sheriff, R. Sakthivel
2024 J jnl
The Artificial Neuron: Built From Nanosheet Transistors to Achieve Ultra Low Power Consumption.
IEEE Access
I. Munavar Sheriff, R. Sakthivel
2022 J jnl
Mathematical and Circuit Level Analysis Interpretation and Recommendations on Neuron Models.
J. Circuits Syst. Comput.
I. Munavar Sheriff, R. Sakthivel
2022 J jnl
Neuron Network with a Synapse of CMOS transistor and Anti-Parallel Memristors for Low power Implementations.
J. Circuits Syst. Comput.
V. Keerthy Rai, R. Sakthivel
2020 J jnl
An efficient hardware implementation of the elliptic curve cryptographic processor over prime field, .
Int. J. Circuit Theory Appl.
Thirumalesu Kudithi, R. Sakthivel
2020 J jnl
Design of Artificial Neuron Network with Synapse Utilizing Hybrid CMOS Transistors with Memristor for Low Power Applications.
J. Circuits Syst. Comput.
V. Keerthy Rai, R. Sakthivel
2020 J jnl
Superior Implementation of Accelerated QR Decomposition for Ultrasound Imaging.
IEEE Access
Sreejeesh S. G., R. Sakthivel, Jayaraj U. Kidav
2019 J jnl
High-performance ECC processor architecture design for IoT security applications.
J. Supercomput.
Thirumalesu Kudithi, R. Sakthivel
2018 — conf
Nonlinear System Modelling Using Programmable Hardware for Soft Computing Applications.
SocProS (2)
M. Vanitha, R. Sakthivel, Mangayarkarasi Ramaiah, Suvarcha Sharma
2014 J jnl
Energy Efficient Low Area Error Tolerant Adder with Higher Accuracy.
Circuits Syst. Signal Process.
R. Sakthivel, Harish M. Kittur
2014 J jnl
Low power high throughput reconfigurable stream cipher hardware VLSI architectures.
Int. J. Inf. Comput. Secur.
R. Sakthivel, M. Vanitha, Harish M. Kittur
2013 J jnl
Design of dynamically reconfigurable fully optimized low power FFT architecture for MC-CDMA receiver.
IEICE Electron. Express
R. Sakthivel, Harish M. Kittur
2012 — conf
Low power energy efficient pipelined multiply-accumulate architecture.
ICACCI
R. Sakthivel, K. Sravanthi, Harish M. Kittur
2025 Best paper conf
Assessing the Effectiveness of the Tigress Obfuscator Against MOPSA and BinaryNinja.
CheckMATE
Nicolò Altamura, Enrico Bragastini, Marco Campion, Mila Dalla Preda
2026 Best paper preprint
ASSEMBLAGE-DEEPHISTORY: A Cross-Build Binary Dataset with Temporal Coverage.
arXiv
Chang Liu, Noah Fleischmann, Nicolò Altamura, Edward Raff, James Holt, Kristopher Micinski