R. Iris Bahar

144 papers A* 10A 27B 5C 5Misc 7Journal 47Unranked 41
YearRankTypeTitle / Venue / Authors
2026 J jnl
Real-Time, Energy-Efficient, Sampling-Based Optimal Control via FPGA Acceleration.
CoRR
Tanmay Desai, Brian Plancher, R. Iris Bahar
2025 A* conf
Robot Planning Under Uncertainty for Object Assembly and Troubleshooting Using Human Causal Models.
ICRA
Semanti Basu, Semir Tatlidil, Moon Hwan Kim, Tiffany Tran, Serena Saxena, Tom Williams, Steven A. Sloman, R. Iris Bahar
2024 — conf
A Midsummer Night's Tree: Efficient and High Performance Secure SCM.
ASPLOS (3)
Samuel Thomas, Kidus Workneh, Jac McCarty, Joseph Izraelevitz, Tamara Lehman, R. Iris Bahar
2024 J jnl
Baobab Merkle Tree for Efficient Secure Memory.
IEEE Comput. Archit. Lett.
Samuel Thomas, Kidus Workneh, Ange-Thierry Ishimwe, Zack McKevitt, Phaedra S. Curlin, R. Iris Bahar, Joseph Izraelevitz, Tamara Lehman
2024 A* conf
Invited: Using Causal Information to Enable More Efficient Robot Operation.
DAC
Semanti Basu, Semir Tatlidil, Moon Hwan Kim, Steven A. Sloman, R. Iris Bahar
2023 — conf
LipoPose: Adapting Cellpose to Lipid Nanoparticle Segmentation.
BIOIMAGING
Semanti Basu, Peter Bajcsy, Thomas E. Cleveland IV, Manuel J. Carrasco, R. Iris Bahar
2022 A conf
A Reconfigurable Hardware Library for Robot Scene Perception.
ICCAD
Yanqi Liu, Anthony Opipari, Odest Chadwicke Jenkins, R. Iris Bahar
2022 — conf
EDAML 2022 Invited Speaker 3: Scalable ML Architectures for Real-time Energy-efficient Computing.
IPDPS Workshops
R. Iris Bahar
2022 — conf
Eliminating Micro-Architectural Side-Channel Attacks using Near Memory Processing.
SEED
Casey Nelson, Joseph Izraelevitz, R. Iris Bahar, Tamara Silbergleit Lehman
2022 B conf
HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures.
SPAA
Jiwon Choe, Andrew Crotty, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
2022 — conf
Towards Hardware Accelerated Garbage Collection with Near-Memory Processing.
HPEC
Samuel Thomas, Jiwon Choe, Ofir Gordon, Erez Petrank, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
2021 A conf
Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits.
ITC
Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, R. Iris Bahar
2021 J jnl
Using Human-Guided Causal Knowledge for More Generalized Robot Task Planning.
CoRR
Semir Tatlidil, Yanqi Liu, Emily Sheetz, R. Iris Bahar, Steven A. Sloman
2020 J jnl
Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation.
CoRR
Yanqi Liu, Giuseppe Calderoni, R. Iris Bahar
2020 A conf
Hardware Acceleration of Robot Scene Perception Algorithms.
ICCAD
Yanqi Liu, Can Eren Derman, Giuseppe Calderoni, R. Iris Bahar
2020 J jnl
Voltage Noise Mitigation With Barrier Approximation.
IEEE Comput. Archit. Lett.
Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu
2020 J jnl
Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond.
CoRR
R. Iris Bahar, Alex K. Jones, Srinivas Katkoori, Patrick H. Madden, Diana Marculescu, Igor L. Markov
2019 — conf
Attacking memory-hard scrypt with near-data-processing.
MEMSYS
Jiwon Choe, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2019 J jnl
Automated High-Level Generation of Low-Power Approximate Computing Circuits.
IEEE Trans. Emerg. Top. Comput.
Kumud Nepal, Soheil Hashemi, Hokchhay Tann, R. Iris Bahar, Sherief Reda
2019 — conf
Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis.
IISWC
Zamshed I. Chowdhury, S. Karen Khatamifard, Zhaoyong Zheng, Tali Moreshet, R. Iris Bahar, Ulya R. Karpuzcu
2019 B conf
Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation.
SPAA
Jiwon Choe, Amy Huang, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
2019 J jnl
Conference Reports: Recap of the 37th Edition of the International Conference on Computer-Aided Design (ICCAD 2018).
IEEE Des. Test
R. Iris Bahar
2019 A conf
GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments.
IROS
Xiaotong Chen, Rui Chen, Zhiqiang Sui, Zhefan Ye, Yanqi Liu, R. Iris Bahar, Odest Chadwicke Jenkins
2019 J jnl
GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments.
CoRR
Xiaotong Chen, Rui Chen, Zhiqiang Sui, Zhefan Ye, Yanqi Liu, R. Iris Bahar, Odest Chadwicke Jenkins
2019 A conf
IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM.
DATE
Dimitra Papagiannopoulou, Sungseob Whang, Tali Moreshet, R. Iris Bahar
2019 J jnl
Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack.
J. Electron. Test.
Yi Sun, Fanchen Zhang, Hui Jiang, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
2019 Misc conf
Special Session: Does Approximation Make Testing Harder (or Easier)?
VTS
R. Iris Bahar, Ulya R. Karpuzcu, Sasa Misailovic
2019 — conf
Test Architecture for Fine Grained Capture Power Reduction.
ICECS
Yi Sun, Hui Jiang, Lakshmi Ramakrishnan, Matan Segal, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
2018 J jnl
A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky
2018 J jnl
Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD).
IEEE Des. Test
Sri Parameswaran, R. Iris Bahar, David Z. Pan
2018 J jnl
Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures.
Int. J. Parallel Program.
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar
2018 A conf
Robust object estimation using generative-discriminative inference for secure robotics applications.
ICCAD
Yanqi Liu, Alessandro Costantini, R. Iris Bahar, Zhiqiang Sui, Zhefan Ye, Shiyang Lu, Odest Chadwicke Jenkins
2018 J jnl
Towards the Simulation Based Design and Validation of Mobile Robotic Cyber-Physical Systems.
J. Low Power Electron.
Christopher B. Harris, R. Iris Bahar
2017 — conf
A Research Tool for the Power and Performance Analysis of Sensor-Based Mobile Robots.
NGCAS
Christopher B. Harris, R. Iris Bahar
2017 — conf
Comprehensive comparison of gradient-based cross-spectral stereo matching generated disparity maps.
MWSCAS
Christopher B. Picardo, Justin G. R. Delva, R. Iris Bahar
2017 J jnl
Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency.
ACM Trans. Embed. Comput. Syst.
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
2017 — conf
Evaluating critical bits in arithmetic operations due to timing violations.
HPEC
Sungseob Whang, Tymani Rachford, Dimitra Papagiannopoulou, Tali Moreshet, R. Iris Bahar
2017 A* conf
Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks.
DAC
Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda
2017 A conf
Understanding the impact of precision quantization on the accuracy and energy of neural networks.
DATE
Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda
2016 A* conf
A fast simulator for the analysis of sub-threshold thermal noise transients.
DAC
Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky
2016 A* conf
A low-power dynamic divider for approximate applications.
DAC
Soheil Hashemi, R. Iris Bahar, Sherief Reda
2016 — conf
Design of Error-Resilient Logic Gates with Reinforcement Using Implications.
ACM Great Lakes Symposium on VLSI
Xijing Han, Marco Donato, R. Iris Bahar, Alexander Zaslavsky, William R. Patterson
2016 B conf
Hardware acceleration of feature detection and description algorithms on low-power embedded platforms.
FPL
Onur Ulusel, Christopher B. Picardo, Christopher B. Harris, Sherief Reda, R. Iris Bahar
2016 J jnl
Runtime Configurable Deep Neural Networks for Energy-Accuracy Trade-off.
CoRR
Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda
2016 Misc conf
Runtime configurable deep neural networks for energy-accuracy trade-off.
CODES+ISSS
Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda
2016 Misc conf
Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems.
CASES
Thomas Carle, Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Maurice Herlihy, R. Iris Bahar
2016 J jnl
Understanding the Impact of Precision Quantization on the Accuracy and Energy of Neural Networks.
CoRR
Soheil Hashemi, Nicholas Anthony, Hokchhay Tann, R. Iris Bahar, Sherief Reda
2016 — conf
Using Existing Reconfigurable Logic in 3D Die Stacks for Test.
NATW
Fanchen Zhang, Yi Sun, Xi Shen, Kundan Nepal, Jennifer Dworak, Theodore W. Manikas, Ping Gui, R. Iris Bahar, Al Crouch, John C. Potter
2015 — conf
A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits.
ACM Great Lakes Symposium on VLSI
Marco Donato, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky
2015 A conf
DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications.
ICCAD
Soheil Hashemi, R. Iris Bahar, Sherief Reda
2015 J jnl
Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems.
ACM Trans. Embed. Comput. Syst.
Dimitra Papagiannopoulou, Giuseppe Capodanno, Tali Moreshet, Maurice Herlihy, R. Iris Bahar
2015 J jnl
Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems.
ACM Trans. Design Autom. Electr. Syst.
R. Iris Bahar, Alex K. Jones, Yuan Xie
2015 — conf
Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution.
ACM Great Lakes Symposium on VLSI
Dimitra Papagiannopoulou, Andrea Marongiu, Tali Moreshet, Luca Benini, Maurice Herlihy, R. Iris Bahar
2015 J jnl
Repairing a 3-D Die-Stack Using Available Programmable Logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Kundan Nepal, Soha Alhelaly, Jennifer Dworak, R. Iris Bahar, Theodore W. Manikas, Ping Guikundan
2014 A conf
ABACUS: A technique for automated behavioral synthesis of approximate computing circuits.
DATE
Kumud Nepal, Yueting Li, R. Iris Bahar, Sherief Reda
2014 J jnl
Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators.
ACM Trans. Reconfigurable Technol. Syst.
Onur Ulusel, Kumud Nepal, R. Iris Bahar, Sherief Reda
2014 — conf
Speculative synchronization for coherence-free embedded NUMA architectures.
ICSAMOS
Dimitra Papagiannopoulou, Tali Moreshet, Andrea Marongiu, Luca Benini, Maurice Herlihy, R. Iris Bahar
2013 — conf
"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation.
MSE
R. Iris Bahar, Alex K. Jones, Srinivas Katkoori, Patrick H. Madden, Diana Marculescu, Igor L. Markov
2013 — conf
Built-in Self-Repair in a 3D die stack using programmable logic.
DFTS
Kundan Nepal, Xi Shen, Jennifer Dworak, Theodore W. Manikas, R. Iris Bahar
2013 — conf
Flexible data allocation for scratch-pad memories to reduce NBTI effects.
ISQED
Dimitra Papagiannopoulou, Patipan Prasertsom, R. Iris Bahar
2013 — conf
Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs.
MES
Dimitra Papagiannopoulou, R. Iris Bahar, Tali Moreshet, Maurice Herlihy, Andrea Marongiu, Luca Benini
2012 — conf
A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic.
ACM Great Lakes Symposium on VLSI
Marco Donato, Fabio Cremona, Warren Jin, R. Iris Bahar, William R. Patterson, Alexander Zaslavsky, Joseph L. Mundy
2012 Misc conf
Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators.
FCCM
Kumud Nepal, Onur Ulusel, R. Iris Bahar, Sherief Reda
2012 — conf
High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System.
ASAP
Roto Le, Joseph L. Mundy, R. Iris Bahar
2012 J jnl
NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems.
J. Electron. Test.
Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera
2012 J jnl
Using implications to choose tests through suspect fault identification.
ACM Trans. Design Autom. Electr. Syst.
Jennifer Dworak, Kundan Nepal, Nuno Alves, Yiwen Shi, Nicholas Imbriglia, R. Iris Bahar
2011 — conf
A novel parallel Tier-1 coder for JPEG2000 using GPUs.
SASP
Roto Le, R. Iris Bahar, Joseph L. Mundy
2011 B conf
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis.
ETS
Nuno Alves, Yiwen Shi, Nicholas Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar
2011 Misc conf
Enhancing online error detection through area-efficient multi-site implications.
VTS
Nuno Alves, Yiwen Shi, Jennifer Dworak, R. Iris Bahar, Kundan Nepal
2011 — conf
NBTI-aware data allocation strategies for scratchpad memory based embedded systems.
LATW
Cesare Ferri, Dimitra Papagiannopoulou, R. Iris Bahar, Andrea Calimera
2011 Misc conf
SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs.
CODES+ISSS
Cesare Ferri, Andrea Marongiu, Benjamin Lipton, R. Iris Bahar, Tali Moreshet, Luca Benini, Maurice Herlihy
2011 J jnl
Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems.
J. Electron. Test.
Desta Tadesse, R. Iris Bahar, Joel Grodstein
2010 J jnl
A Cost Effective Approach for Online Error Detection Using Invariant Relationships.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Nuno Alves, Alison Buben, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
2010 J jnl
Dual-V
Microelectron. J.
Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino
2010 J jnl
Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems.
J. Parallel Distributed Comput.
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2010 — conf
Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems.
HiPEAC
Cesare Ferri, Samantha Wood, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2010 — conf
Improving the testability and reliability of sequential circuits with invariant logic.
ACM Great Lakes Symposium on VLSI
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
2010 — conf
Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices.
ACM Great Lakes Symposium on VLSI
Pooya Jannaty, Florian C. Sabou, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2010 — ed.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010
ACM Great Lakes Symposium on VLSI
R. Iris Bahar, Fabrizio Lombardi, David Atienza, Erik Brunvand
2010 J jnl
Temperature-Insensitive Dual- V
IEEE Trans. Very Large Scale Integr. Syst.
Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino
2009 A conf
AutoRex: An automated post-silicon clock tuning tool.
ITC
Desta Tadesse, Joel Grodstein, R. Iris Bahar
2009 A conf
Compacting test vector sets via strategic use of implications.
ICCAD
Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan Nepal
2009 A conf
Detecting errors using multi-cycle invariance information.
DATE
Nuno Alves, Kundan Nepal, Jennifer Dworak, R. Iris Bahar
2009 — conf
Energy-optimal synchronization primitives for single-chip multi-processors.
ACM Great Lakes Symposium on VLSI
Cesare Ferri, R. Iris Bahar, Mirko Loghi, Massimo Poncino
2009 A conf
High-performance, cost-effective heterogeneous 3D FPGA architectures.
FPGA
Roto Le, Sherief Reda, R. Iris Bahar
2009 — conf
High-performance, cost-effective heterogeneous 3D FPGA architectures.
ACM Great Lakes Symposium on VLSI
Roto Le, Sherief Reda, R. Iris Bahar
2009 J jnl
Introduction to special section: Best of NANOARCH 2008.
ACM J. Emerg. Technol. Comput. Syst.
R. Iris Bahar
2009 — ed.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009
ACM Great Lakes Symposium on VLSI
Fabrizio Lombardi, Sanjukta Bhanja, Yehia Massoud, R. Iris Bahar
2009 A conf
Reducing the leakage and timing variability of 2D ICcs using 3D ICs.
ISLPED
Sherief Reda, Aung Si, R. Iris Bahar
2008 — conf
Energy efficient synchronization techniques for embedded architectures.
ACM Great Lakes Symposium on VLSI
Cesare Ferri, Amber Viescas, Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2008 Misc conf
Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation.
VTS
Desta Tadesse, R. Iris Bahar, Joel Grodstein
2008 J jnl
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies.
ACM J. Emerg. Technol. Comput. Syst.
R. Iris Bahar, Krishnendu Chakrabarty
2008 J jnl
Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies.
ACM Trans. Design Autom. Electr. Syst.
R. Iris Bahar, Krishnendu Chakrabarty
2008 J jnl
Parametric yield management for 3D ICs: Models and strategies for improvement.
ACM J. Emerg. Technol. Comput. Syst.
Cesare Ferri, Sherief Reda, R. Iris Bahar
2008 A conf
Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits.
ISLPED
Andrea Calimera, R. Iris Bahar, Enrico Macii, Massimo Poncino
2008 — conf
Temperature-insensitive synthesis using multi-vt libraries.
ACM Great Lakes Symposium on VLSI
Andrea Calimera, Enrico Macii, Massimo Poncino, R. Iris Bahar
2008 J jnl
Thermal-Aware Design Techniques for Nanometer CMOS Circuits.
J. Low Power Electron.
Andrea Calimera, Karthik Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, R. Iris Bahar, Alberto Macii, Enrico Macii, Massimo Poncino
2008 A conf
Using Implications for Online Error Detection.
ITC
Kundan Nepal, Nuno Alves, Jennifer Dworak, R. Iris Bahar
2007 J jnl
A hardware/software framework for supporting transactional memory in a MPSoC environment.
SIGARCH Comput. Archit. News
Cesare Ferri, Tali Moreshet, R. Iris Bahar, Luca Benini, Maurice Herlihy
2007 A conf
Accurate timing analysis using SAT and pattern-dependent delay models.
DATE
Desta Tadesse, D. Sheffield, E. Lenge, R. Iris Bahar, Joel Grodstein
2007 J jnl
Architectures for Silicon Nanoelectronics and Beyond.
Computer
R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram
2007 J jnl
Designing Nanoscale Logic Circuits Based on Markov Random Fields.
J. Electron. Test.
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2007 A conf
Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits.
DATE
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2007 A conf
Strategies for improving the parametric yield and profits of 3D ICs.
ICCAD
Cesare Ferri, Sherief Reda, R. Iris Bahar
2007 — conf
Thermally-induced soft errors in nanoscale CMOS circuits.
NANOARCH
Hua Li, Joseph L. Mundy, William R. Patterson, Dimitrios Kazazis, Alexander Zaslavsky, R. Iris Bahar
2006 A* conf
A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.
DAC
Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss
2006 A conf
Designing MRF based error correcting circuits for memory elements.
DATE
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2006 B conf
Energy implications of multiprocessor synchronization.
SPAA
Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2006 J jnl
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits.
IEEE Micro
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2006 — conf
Optimizing noise-immune nanoscale circuits using principles of Markov random fields.
ACM Great Lakes Symposium on VLSI
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2006 J jnl
Timing analysis for full-custom circuits using symbolic DC formulations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hui-Yuan Song, Kundan Nepal, R. Iris Bahar, Joel Grodstein
2006 C conf
Trends and Future Directions in Nano Structure Based Computing and Fabrication.
ICCD
R. Iris Bahar
2005 A* conf
Designing logic circuits for probabilistic computation in the presence of noise.
DAC
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky
2005 A conf
Energy reduction in multiprocessor systems using transactional memory.
ISLPED
Tali Moreshet, R. Iris Bahar, Maurice Herlihy
2005 J jnl
Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale.
IEEE Des. Test Comput.
R. Iris Bahar, Mehdi Baradaran Tahoori, Sandeep K. Shukla, Fabrizio Lombardi
2005 J jnl
Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
R. Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein
2004 J jnl
A low-power in-order/out-of-order issue queue.
ACM Trans. Archit. Code Optim.
Yu Bai, R. Iris Bahar
2004 J jnl
Effects of speculation on performance and issue queue design.
IEEE Trans. Very Large Scale Integr. Syst.
Tali Moreshet, R. Iris Bahar
2004 C conf
Fetch Halting on Critical Load Misses.
ICCD
Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss
2004 — conf
RESTA: a robust and extendable symbolic timing analysis tool.
ACM Great Lakes Symposium on VLSI
Kundan Nepal, Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
2004 C conf
Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm.
ICCD
Yu Bai, R. Iris Bahar
2003 — conf
A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors.
ISVLSI
Yu Bai, R. Iris Bahar
2003 A conf
A Probabilistic-Based Design Methodology for Nanoscale Computation.
ICCAD
R. Iris Bahar, Joseph L. Mundy, Jie Chen
2003 — conf
Combining Software and Hardware Monitoring for Improved Power and Performance Tuning.
Interaction between Compilers and Computer Architectures
Eric Chi, A. Michael Salem, R. Iris Bahar, Richard S. Weiss
2003 A* conf
Power-aware issue queue design for speculative instructions.
DAC
Tali Moreshet, R. Iris Bahar
2003 C conf
Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current.
ICCD
Hui-Yuan Song, S. Bohidar, R. Iris Bahar, Joel Grodstein
2002 — conf
Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations.
IWLS
Hui-Yuan Song, R. Iris Bahar, Joel Grodstein
2001 A* conf
Power and energy reduction via pipeline balancing.
ISCA
R. Iris Bahar, Srilatha Manne
2000 — conf
Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors.
PACS
Roberto Maro, Yu Bai, R. Iris Bahar
2000 J jnl
Power optimization of technology-dependent circuits based on symbolic computation of logic implications.
ACM Trans. Design Autom. Electr. Syst.
R. Iris Bahar, Ernest T. Lampe, Enrico Macii
1999 J jnl
A comparison of software code reordering and victim buffers.
SIGARCH Comput. Archit. News
R. Iris Bahar, Brad Calder, Dirk Grunwald
1999 C conf
The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency.
ICCD
Brian R. Fisk, R. Iris Bahar
1998 A conf
Power and performance tradeoffs using various caching strategies.
ISLPED
R. Iris Bahar, Gianluca Albera, Srilatha Manne
1997 J jnl
Algebraic Decision Diagrams and Their Applications.
Formal Methods Syst. Des.
R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
1997 J jnl
Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
1996 A conf
Symbolic computation of logic implications for technology-dependent low-power synthesis.
ISLPED
R. Iris Bahar, M. Burns, Gary D. Hachtel, Enrico Macii, H. Shin, Fabio Somenzi
1995 A conf
Boolean techniques for low power driven re-synthesis.
ICCAD
R. Iris Bahar, Fabio Somenzi
1995 — conf
CMOS dynamic power estimation based on collapsible current source transistor modeling.
ISLPD
Abelardo Pardo, R. Iris Bahar, Srilatha Manne, Peter Feldmann, Gary D. Hachtel, Fabio Somenzi
1995 A* conf
Computing the Maximum Power Cycles of a Sequential Circuit.
DAC
Srilatha Manne, Abelardo Pardo, R. Iris Bahar, Gary D. Hachtel, Fabio Somenzi, Enrico Macii, Massimo Poncino
1994 A conf
A symbolic method to reduce power consumption of circuits containing false paths.
ICCAD
R. Iris Bahar, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
1994 — conf
An ADD-based algorithm for shortest path back-tracing of large graphs.
Great Lakes Symposium on VLSI
R. Iris Bahar, Gary D. Hachtel, Abelardo Pardo, Massimo Poncino, Fabio Somenzi
1994 — conf
Timing Analysis of Combinational Circuits using ADD's.
EDAC-ETC-EUROASIC
R. Iris Bahar, Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Fabio Somenzi
1993 A conf
Algebraic decision diagrams and their applications.
ICCAD
R. Iris Bahar, Erica A. Frohm, Charles M. Gaona, Gary D. Hachtel, Enrico Macii, Abelardo Pardo, Fabio Somenzi
1992 J jnl
A 100-MHz macropipelined VAX microprocessor.
IEEE J. Solid State Circuits
Roy W. Badeau, R. Iris Bahar, Debra Bemstein, Larry L. Biro, William J. Bowhill, John F. Brown III, Michael A. Case, Ruben W. Castelino, Elizabeth M. Cooper, Maureen A. Delaney, David R. Deverell, John H. Edmondson, John J. Ellis, Timothy C. Fischer, Thomas F. Fox, Mary K. Gowan, Paul E. Gronowski, William V. Herrick, Anil K. Jain, Jeanne E. Meyer, Daniel G. Miner, Hamid Partovi, Victor Peng, Ronald P. Preston, Chandrasekhara Somanathan, Rebecca L. Stamm, Stephen C. Thierauf, G. Michael Uhler, Nicholas D. Wade, William R. Wheeler