R. D. (Shawn) Blanton

83 papers A* 7A 23B 2C 2Misc 16Journal 25Unranked 7

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators. CoRR Prabhu Vellaisamy, Harideep Nair, Di Wu, R. D. (Shawn) Blanton, John Paul Shen
2026	J	`jnl`	TaxBreak: Unmasking the Hidden Costs of LLM Inference Through Overhead Decomposition. CoRR Prabhu Vellaisamy, Shreesh Tripathi, Vignesh Natarajan, Surya Santhan Thenarasu, R. D. (Shawn) Blanton, John Paul Shen
2025	J	`jnl`	BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks. CoRR Wei Li, Yang Zou, Christopher Ellis, Ruben Purdy, R. D. (Shawn) Blanton, José M. F. Moura
2025	A	`conf`	IC-PEPR: PEPR Testing Goes Intra-Cell. ITC Chris Nigh, Ruben Purdy, Wei Li, Subhasish Mitra, R. D. (Shawn) Blanton
2024	J	`jnl`	tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit. CoRR Prabhu Vellaisamy, Harideep Nair, Joseph Finn, Manav Trivedi, Albert Chen, Anna Li, Tsung-Han Lin, Perry H. Wang, R. D. (Shawn) Blanton, John Paul Shen
2023	A*	`conf`	Global Floorplanning via Semidefinite Programming. DAC Wei Li, Fangzhou Wang, José M. F. Moura, R. D. (Shawn) Blanton
2020	J	`jnl`	Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer. ACM Trans. Design Autom. Electr. Syst. Qicheng Huang, Chenlei Fang, Soumya Mittal, R. D. (Shawn) Blanton
2019	A	`conf`	Characterization of Locked Combinational Circuits via ATPG. ITC Danielle Duvalsaint, Xiaoxiao Jin, Benjamin Niewenhuis, R. D. (Shawn) Blanton
2019	A*	`conf`	FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference. DAC Ruizhou Ding, Zeye Liu, Ting-Wu Chin, Diana Marculescu, R. D. (Shawn) Blanton
2019	A	`conf`	Improving Test Chip Design Efficiency via Machine Learning. ITC Zeye Liu, Qicheng Huang, Chenlei Fang, R. D. (Shawn) Blanton
2018	B	`conf`	Detection of IJTAG attacks using LDPC-based feature reduction and machine learning. ETS Xuanle Ren, R. D. (Shawn) Blanton, Vítor Grade Tavares
2018	J	`jnl`	LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. CoRR Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton
2018	J	`jnl`	Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs. ACM Trans. Reconfigurable Technol. Syst. Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu
2018	Misc	`conf`	NOIDA: Noise-resistant Intra-cell Diagnosis. VTS Soumya Mittal, R. D. (Shawn) Blanton
2018	—	`conf`	Quantized deep neural networks for energy efficient hardware-based inference. ASP-DAC Ruizhou Ding, Zeye Liu, R. D. (Shawn) Blanton, Diana Marculescu
2017	—	`conf`	LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. ACM Great Lakes Symposium on VLSI Ruizhou Ding, Zeye Liu, Rongye Shi, Diana Marculescu, R. D. (Shawn) Blanton
2017	B	`conf`	Multiple-defect diagnosis for Logic Characterization Vehicles. ETS Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton
2017	—	`conf`	PADLOC: Physically-Aware Defect Localization and Characterization. ATS Soumya Mittal, R. D. (Shawn) Blanton
2017	—	`conf`	Random Forest Architectures on FPGA for Multiple Applications. ACM Great Lakes Symposium on VLSI Xiang Lin, R. D. (Shawn) Blanton, Donald E. Thomas
2017	Misc	`conf`	Test-set reordering for improving diagnosability. VTS Cheng Xue, R. D. (Shawn) Blanton
2016	A	`conf`	Achieving 100% cell-aware coverage by design. DATE Zeye Liu, Ben Niewenhuis, Soumya Mittal, R. D. (Shawn) Blanton
2016	J	`jnl`	Ensemble Reduction via Logic Minimization. ACM Trans. Design Autom. Electr. Syst. Hongfei Wang, R. D. (Shawn) Blanton
2016	A	`conf`	Logic characterization vehicle design reflection via layout rewiring. ITC Phillip Fynan, Zeye Liu, Benjamin Niewenhuis, Soumya Mittal, Marcin Strajwas, R. D. (Shawn) Blanton
2016	A	`conf`	Test chip design for optimal cell-aware diagnosability. ITC Soumya Mittal, Zeye Liu, Ben Niewenhuis, R. D. (Shawn) Blanton
2015	C	`conf`	A one-pass test-selection method for maximizing test coverage. ICCD Cheng Xue, R. D. (Shawn) Blanton
2015	A	`conf`	Design reflection for optimal test-chip implementation. ITC R. D. (Shawn) Blanton, Benjamin Niewenhuis, Zeye (Dexter) Liu
2015	A	`conf`	Detection of illegitimate access to JTAG via statistical learning in chip. DATE Xuanle Ren, Vítor Grade Tavares, R. D. (Shawn) Blanton
2014	J	`jnl`	Design-for-Manufacturability Assessment for Integrated Circuits Using RADAR. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wing Chiu Tam, R. D. (Shawn) Blanton
2014	—	`conf`	Physically-Aware Diagnostic Resolution. ATS John A. Porche, R. D. (Shawn) Blanton
2014	—	`conf`	Predicting IC Defect Level Using Diagnosis. ATS Cheng Xue, R. D. (Shawn) Blanton
2014	J	`jnl`	Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis. ACM Trans. Design Autom. Electr. Syst. Sounil Biswas, Hongfei Wang, R. D. (Shawn) Blanton
2012	J	`jnl`	Diagnosis-Assisted Adaptive Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiaochun Yu, R. D. (Shawn) Blanton
2012	A	`conf`	On-chip diagnosis for early-life and wear-out failures. ITC Matthew Beckler, R. D. (Shawn) Blanton
2012	J	`jnl`	Physically-Aware N-Detect Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yen-Tzu Lin, Osei Poku, R. D. (Shawn) Blanton, Phil Nigh, Peter Lloyd, Vikram Iyengar
2012	J	`jnl`	SLIDER: Simulation of Layout-Injected Defects for Electrical Responses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wing Chiu Tam, R. D. (Shawn) Blanton
2012	J	`jnl`	Yield Learning Through Physically Aware Diagnosis of IC-Failure Populations. IEEE Des. Test Comput. R. D. (Shawn) Blanton, Wing Chiu Tam, Xiaochun Yu, Jeffrey E. Nelson, Osei Poku
2011	A	`ed.`	2011 IEEE International Test Conference, ITC 2011, Anaheim, CA, USA, September 20-22, 2011 ITC Bill Eklow, R. D. (Shawn) Blanton
2011	J	`jnl`	METER: Measuring Test Effectiveness Regionally. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yen-Tzu Lin, R. D. (Shawn) Blanton
2011	A	`conf`	Physically-aware analysis of systematic defects in integrated circuits. ITC Wing Chiu Tam, R. D. (Shawn) Blanton
2011	A	`conf`	Statistical defect-detection analysis of test sets using readily-available tester data. ICCAD Xiaochun Yu, R. D. (Shawn) Blanton
2011	A*	`conf`	To DFM or not to DFM? DAC Wing Chiu Tam, R. D. (Shawn) Blanton
2010	Misc	`conf`	Evaluating yield and testing impact of sub-wavelength lithography. VTS Wing Chiu Tam, R. D. (Shawn) Blanton, Wojciech Maly
2009	A*	`conf`	Automated failure population creation for validating integrated circuit diagnosis methods. DAC Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton
2009	A	`conf`	Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. ICCAD Xin Li, Rob A. Rutenbar, R. D. (Shawn) Blanton
2008	—	`conf`	Automated Standard Cell Library Analysis for Improved Defect Modeling. ISQED Jason G. Brown, R. D. (Shawn) Blanton
2008	A*	`conf`	Multiple defect diagnosis using no assumptions on failing pattern characteristics. DAC Xiaochun Yu, R. D. (Shawn) Blanton
2008	A*	`conf`	Precise failure localization using automated layout analysis of diagnosis candidates. DAC Wing Chiu Tam, Osei Poku, R. D. (Shawn) Blanton
2008	Misc	`conf`	Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data. VTS Sounil Biswas, R. D. (Shawn) Blanton
2007	J	`jnl`	A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology. J. Electron. Test. Jason G. Brown, R. D. (Shawn) Blanton
2007	J	`jnl`	Specification Test Compaction for Analog Circuits and MEMS CoRR Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi
2006	Misc	`conf`	Exploiting Regularity for Inductive Fault Analysis. VTS Jason G. Brown, R. D. (Shawn) Blanton
2006	J	`jnl`	Extracting Defect Density and Size Distributions from Product ICs. IEEE Des. Test Comput. Jeffrey E. Nelson, Thomas Zanon, Jason G. Brown, Osei Poku, R. D. (Shawn) Blanton, Wojciech Maly, Brady Benware, Chris Schuermyer
2006	A	`conf`	Extraction of defect density and size distributions from wafer sort test results. DATE Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jason G. Brown, N. Patil, Wojciech Maly, R. D. (Shawn) Blanton
2006	J	`jnl`	Inductive fault analysis of surface-micromachined MEMS. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tao Jiang, R. D. (Shawn) Blanton
2006	A*	`conf`	Multiple-detect ATPG based on physical neighborhoods. DAC Jeffrey E. Nelson, Jason G. Brown, Rao Desineni, R. D. (Shawn) Blanton
2005	Misc	`conf`	Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction. VTS Rao Desineni, R. D. (Shawn) Blanton
2005	A	`conf`	Specification Test Compaction for Analog Circuits and MEMS. DATE Sounil Biswas, Peng Li, R. D. (Shawn) Blanton, Larry T. Pileggi
2005	Misc	`conf`	Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. VLSI Design R. D. (Shawn) Blanton, Subhasish Mitra
2004	A	`conf`	Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. ITC Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary
2004	A	`conf`	CAEN-BIST: Testing the NanoFabric. ITC Jason G. Brown, R. D. (Shawn) Blanton
2004	Misc	`conf`	Generalized Sensitization using Fault Tuples. VTS Sounil Biswas, Kumar N. Dwarakanath, R. D. (Shawn) Blanton
2004	Misc	`conf`	Multi-Modal Built-In Self-Test for Symmetric Microsystems. VTS Nilmoni Deb, R. D. (Shawn) Blanton
2003	A	`conf`	ATPG for Noise-Induced Switch Failures in Domino Logic. ICCAD Rahul Kundu, R. D. (Shawn) Blanton
2003	A	`conf`	Analyzing the Effectiveness of Multiple-Detect Test Sets. ITC R. D. (Shawn) Blanton, Kumar N. Dwarakanath, Anirudh B. Shah
2003	A	`conf`	Deformations of IC Structure in Test and Yield Learning. ITC Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey
2003	A	`conf`	Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk. ITC Rahul Kundu, R. D. (Shawn) Blanton
2003	A	`conf`	Progressive Bridge Identification. ITC Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton
2002	A	`conf`	Built-In Self Test of CMOS-MEMS Accelerometers. ITC Nilmoni Deb, R. D. (Shawn) Blanton
2002	Misc	`conf`	Exploiting Dominance and Equivalence using Fault Tuples. VTS Kumar N. Dwarakanath, R. D. (Shawn) Blanton
2002	Misc	`conf`	SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? VTS Salvador Mir, H. Bederr, R. D. (Shawn) Blanton, Hans G. Kerkhoff, H. J. Klim
2002	Misc	`conf`	Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits. VTS Rahul Kundu, R. D. (Shawn) Blanton
2001	Misc	`conf`	Testing of Dynamic Logic Circuits Based on Charge Sharing. VTS Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton
2000	J	`jnl`	A Buffer-Oriented Methodology for Microarchitecture Validation. J. Electron. Test. Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
2000	J	`jnl`	Effectiveness of Microarchitecture Test Program Generation. IEEE Des. Test Comput. Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
1999	J	`jnl`	An integrated functional performance simulator. IEEE Micro Candice Bechem, Jonathan Combs, Noppanunt Utamaphethai, Bryan Black, R. D. (Shawn) Blanton, John Paul Shen
1999	J	`jnl`	Guest Editors' Introduction. IEEE Des. Test Comput. Bernard Courtois, R. D. (Shawn) Blanton
1999	J	`jnl`	Hierarchical Design and Test of Integrated Microsystems. IEEE Des. Test Comput. Tamal Mukherjee, Gary K. Fedder, R. D. (Shawn) Blanton
1999	Misc	`conf`	IDDQ-Testability of Tree Circuits. VLSI Design R. D. (Shawn) Blanton
1999	Misc	`conf`	Superscalar Processor Validation at the Microarchitecture Level. VLSI Design Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
1998	C	`conf`	Using regression analysis for GA-based ATPG parameter optimization. ICCD William E. Dougherty, R. D. (Shawn) Blanton
1997	J	`jnl`	Testability Properties of Divergent Trees. J. Electron. Test. R. D. (Shawn) Blanton, John P. Hayes
1996	Misc	`conf`	Design of a fast, easily testable ALU. VTS R. D. (Shawn) Blanton, John P. Hayes
1995	—	`—`	Design and testing of regular circuits. R. D. (Shawn) Blanton